Inventor

TRAN HIEP V

US43 patents

⚠️ This page may combine multiple inventors who share the name “TRAN HIEP V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN HIEP V

TEXAS INSTRUMENTS INC

Hierarchical DRAM array with grouped I/O lines and high speed sensing circuit

Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit

DRAM with sub data lines and match lines for test

Sense amplifier and method for sensing the outputs of static random access memory cells

High performance bipolar differential sense amplifier in a BiCMOS SRAM

Bipolar-CMOS static ram memory device

Virtual ground circuit for reducing SRAM standby power

Address match scheme for DRAM redundancy scheme

BiCMOS static memory with improved performance stability

High-speed DRAM sense amp with high noise immunity

Battery backup bus scheme for an ECL BiCMOS SRAM

Bipolar-CMOS static random access memory device with bit line bias control

BiCMOS static memory with improved performance stability

BICMOS TTL input buffer

Bitline pull-up circuit for a BiCMOS read/write memory

Sensing and decoding scheme for a BiCMOS read/write memory

Fast rise time booting circuit

Programmable stackable memory array system

Jitter reduction circuit

Apparatus and method for an error signal compression technique in a fast adaptive equalizer circuit

High speed signal driving scheme

Charge mirror circuit

Data converter with vertical resistor meander

High speed, low power clocking sense amplifier

Method to reduce burn-in time and inducing infant failure

Self latching input buffer

Self latching input buffer

High speed signal driving scheme

High voltage lateral transistor

BiCMOS TTL input buffer

Darlington BiCMOS driver circuit

BiCMOS reference network

Darlington BiCMOS driver circuit

Pass gate with low transistor junction breakdown susceptibility

Self-selecting precharged domino logic circuit

Virtual ground circuit for reducing SRAM standby power

Stacked cache memory system and method

Stacked sense-amp cache memory system and method

Bicmos TTL output driver circuit

Dram sensing scheme

THOMSON COMPONENTS MOSTEK CORP

Memory cell leakage detection circuit

CMOS memory arrangement with reduced data line compacitance

TRAN HIEP V

Sensing and decoding scheme for a bicmos read/write memory