Inventor · disambiguated record
Deepak K. Pai
Also filed as: PAI DEEPAK · PAI DEEPAK K · PAI DEEPAK KESHAV
22 granted patents·2 pending applications·321 citations·filing 1993–2013
95Inventor score
Files withGEN DYNAMICS ADVANCED INF SYS14GEN DYNAMICS INF SYSTEMS INC4PAI DEEPAK K3CERIDAN CORP1GEN DYNAMICS INFORMATION1
Top patents by PatentIndex Score
24 records- 0184US7684205B2System and method of using a compliant lead interposerGEN DYNAMICS ADVANCED INF SYS·Filed 2006·Granted Mar 23, 2010·10 cites·13 claims
- 0284US7614341B1Apparatus and method for a segmented squeegee for stencilingGEN DYNAMICS ADVANCED INF SYS·Filed 2005·Granted Nov 10, 2009·7 cites·16 claims
- 0384US5786238ALaminated multilayer substratesGEN DYNAMICS INFORMATION·Filed 1997·Granted Jul 28, 1998·106 cites·10 claims
- 0483US6742247B2Process for manufacturing laminated high layer count printed circuit boardsGEN DYNAMICS ADVANCED INF SYS·Filed 2003·Granted Jun 1, 2004·25 cites·18 claims
- 0581US8549737B2Method of connecting a grid array package to a printed circuit boardPAI DEEPAK K·Filed 2010·Granted Oct 8, 2013·5 cites·9 claims
- 0681US5953816AProcess of making interposers for land grip arraysGEN DYNAMICS INF SYSTEMS INC·Filed 1997·Granted Sep 21, 1999·53 cites·15 claims
- 0776US7892441B2Method and apparatus to change solder pad size using a differential pad platingGEN DYNAMICS ADVANCED INF SYS·Filed 2007·Granted Feb 22, 2011·6 cites·21 claims
- 0875US8726498B2Methods for filling holes in printed wiring boardsPAI DEEPAK KESHAV·Filed 2010·Granted May 20, 2014·5 cites·5 claims
- 0974US7490402B2Technique for laminating multiple substratesGEN DYNAMICS ADVANCED INF SYS·Filed 2007·Granted Feb 17, 2009·4 cites·8 claims
- 1071US5986339ALaminated multilayer substratesGEN DYNAMICS INF SYSTEMS INC·Filed 1998·Granted Nov 16, 1999·41 cites·6 claims
- 1168US6856008B2Laminated multilayer packageGEN DYNAMICS ADVANCED INF SYS·Filed 2003·Granted Feb 15, 2005·10 cites·41 claims
- 1257US7503767B2Method and apparatus for compliantly connecting stack of high-density electronic modules in harsh environmentsGEN DYNAMICS ADVANCED INF SYS·Filed 2006·Granted Mar 17, 2009·5 cites·22 claims
- 1357US7282787B2Laminated multiple substratesGEN DYNAMICS ADVANCED INF SYS·Filed 2004·Granted Oct 16, 2007·5 cites·7 claims
- 1457US2009250506A1Apparatus and methods of attaching hybrid vlsi chips to printed wiring boardsGEN DYNAMICS ADVANCED INF SYS·Filed 2009·Application pending·0 cites
- 1555US8028403B2Method for forming laminated multiple substratesGEN DYNAMICS ADVANCED INF SYS·Filed 2009·Granted Oct 4, 2011·0 cites·8 claims
- 1654US2011101075A1Apparatus and methods of attaching hybrid vlsi chips to printed wiring boardsGEN DYNAMICS ADVANCED INF SYS·Filed 2011·Application pending·0 cites
- 1752US8481862B2Low profile compliant leadsPAI DEEPAK K·Filed 2006·Granted Jul 9, 2013·2 cites·12 claims
- 1848US5746367AMethod and apparatus to wick solder from conductive surfacesCERIDAN CORP·Filed 1996·Granted May 5, 1998·19 cites·10 claims
- 1947US7818879B2Method and apparatus for compliantly connecting stack of high-density electronic modules in harsh environmentsGEN DYNAMICS ADVANCED INF SYS·Filed 2009·Granted Oct 26, 2010·1 cites·7 claims
- 2044US8196291B2Method for manufacturing leadsPAI DEEPAK K·Filed 2007·Granted Jun 12, 2012·0 cites·16 claims
- 2142US9318350B2Method and apparatus for converting commerical off-the-shelf (COTS) thin small-outline package (TSOP) components into rugged off-the-shelf (ROTS) componentsGEN DYNAMICS ADVANCED INF SYS·Filed 2013·Granted Apr 19, 2016·0 cites·29 claims
- 2242US7802360B2Methods for filling holes in printed wiring boardsGEN DYNAMICS ADVANCED INF SYS·Filed 2004·Granted Sep 28, 2010·1 cites·9 claims
- 2341US5740954AApparatus for attaching/detaching a land grid array component to a circuit boardGEN DYNAMICS INF SYSTEMS INC·Filed 1996·Granted Apr 21, 1998·13 cites·6 claims
- 2431US5871868AApparatus and method for machining conductive structures on substratesGEN DYNAMICS INF SYSTEMS INC·Filed 1993·Granted Feb 16, 1999·3 cites·11 claims
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