Inventor

GEMMEKE TOBIAS

DE19 patents

⚠️ This page may combine multiple inventors who share the name “GEMMEKE TOBIAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GEMMEKE TOBIAS

IBM

Method and system for data dependent performance increment and power reduction

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

Method and system for verifying the equivalence of digital circuits

Reducing register file leakage current within a processor

Formally deriving a minimal clock-gating scheme

Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes

Binary logic unit and method to operate a binary logic unit

System and method for scanning sequential logic elements

Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing

Method of operand width reduction to enable usage of narrower saturation adder

Circuit design methodology to reduce leakage power

STICHTING IMEC NEDERLAND

Method and apparatus for monitoring timing of critical paths

Memory control system for a non-volatile memory and control method

Circuit and method for detection and compensation of transistor mismatch

GEMMEKE TOBIAS

Permute unit and method to operate a permute unit

Binary logic unit and method to operate a binary logic unit

Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance