Circuit and method for detection and compensation of transistor mismatch

Abstract

The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.

The invention claimed is: 
     
       1. A detection circuit formed as part of an integrated circuit, the detection circuit comprising:
 a signal generator configured to generate a reference signal; and 
 an amplification circuit comprising a p-channel transistor and an n-channel transistor, the amplification circuit being affected by a variability also affecting a functional circuit formed as part of the integrated circuit, the variability causing the p-channel transistor and the n-channel transistor to have different respective drive strengths, and the amplification circuit being configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, 
 wherein the reference signal is more insensitive to the variability than the amplified signal. 
 
     
     
       2. The detection circuit of  claim 1 , wherein the variability includes at least one of a process variability, a supply voltage variability, or a temperature variability. 
     
     
       3. The detection circuit of  claim 1 , wherein the signal generator comprises a first component and a second component, wherein the first component and the second component are connected in series, and wherein the first component and the second component are each configured to operate as a conducting diode. 
     
     
       4. The detection circuit of  claim 3 , wherein the first component and the second component are sized such that voltage fluctuations of the reference signal are less than about 1%. 
     
     
       5. The detection circuit of  claim 1 , wherein the signal generator is designed for reducing voltage fluctuations of the generated reference signal in the presence of variabilities. 
     
     
       6. An integrated circuit comprising:
 a signal generator configured to generate a reference signal; 
 a functional circuit; and 
 an amplification circuit comprising a p-channel transistor and an n-channel transistor, the amplification circuit being affected by a variability also affecting the functional circuit, the variability causing the p-channel transistor and the n-channel transistor to have different respective drive strengths, and the amplification circuit being configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, 
 wherein the reference signal is more insensitive to the variability than the amplified signal. 
 
     
     
       7. The integrated circuit of  claim 6 , wherein the variability includes at least one of a process variability, a supply voltage variability, or a temperature variability. 
     
     
       8. The integrated circuit of  claim 6 , wherein the functional circuit comprises an n-channel transistor and a p-channel transistor, the integrated circuit further comprising a control circuit configured to receive the amplified signal and to generate a bias voltage to be applied to the p-channel transistor of the functional circuit and the n-channel transistor of the functional circuit for compensating a difference in respective drive strengths of the p-channel transistor of the functional circuit and the n-channel transistor of the functional circuit. 
     
     
       9. The integrated circuit of  claim 8 , wherein the bias voltage is further applied to the p-channel transistor of the amplification circuit and the n-channel transistor of the amplification circuit for compensating the difference in respective drive strengths of the p-channel transistor of the amplification circuit and the n-channel transistor of the amplification circuit, and wherein the control circuit is further configured to detect that the difference in respective drive strengths of the p-channel transistor of the amplification circuit and the n-channel transistor of the amplification circuit is compensated, based on a voltage change in the amplified signal. 
     
     
       10. The integrated circuit of  claim 8 , wherein the control circuit comprises a memory for storing data representative of the bias voltage, and wherein the control circuit is further configured to select at least one bias voltage that reduces a leakage power of the functional circuit. 
     
     
       11. The integrated circuit of  claim 8 , wherein the control circuit is configured to generate a first bias voltage for the p-channel transistor of the functional circuit and a second bias voltage for the n-channel transistor of the functional circuit. 
     
     
       12. A method comprising:
 generating a reference signal, and 
 amplifying the reference signal with an amplification circuit so as to provide an amplified signal representative of a difference in respective drive strengths of a p-channel transistor of a functional circuit and an n-channel transistor of the functional circuit, wherein the functional circuit is formed as part of an integrated circuit, the integrated circuit being affected by a variability that causes the p-channel transistor and the n-channel transistor to have different respective drive strengths, 
 wherein generating the reference signal comprises generating a reference signal that is more insensitive to the variability than the amplified signal. 
 
     
     
       13. The method of  claim 12 , wherein the amplified signal is also representative of a difference in respective drive strengths of a p-channel transistor of the amplification circuit and an n-channel transistor of the amplification circuit, the method further comprising:
 receiving the amplified signal and generating a bias voltage based on the amplified signal, and providing the bias voltage to a transistor of the functional circuit. 
 
     
     
       14. The method of  claim 13 , wherein the amplified signal is received by a control circuit. 
     
     
       15. The method of  claim 13 , further comprising:
 applying the bias voltage to the p-channel transistor of the amplification circuit or the n-channel transistor of the amplification circuit; and 
 detecting that the difference in drive strength between the p-channel transistor of the amplification circuit and the n-channel transistor of the amplification circuit is compensated. 
 
     
     
       16. The method of  claim 13 , further comprising:
 storing the bias voltage in a memory, and 
 selecting from the memory at least one bias voltage that reduces a leakage power of the functional circuit. 
 
     
     
       17. The method of  claim 13 , wherein generating the bias voltage comprises generating a first bias voltage for a p-channel transistor of at least one of the functional circuit or the amplification circuit and a second bias voltage for an n-channel transistor of at least one of the functional circuit or the amplification circuit.