Inventor

LIU CHI-CHUN

US103 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHI-CHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHI-CHUN

IBM

Grapho-epitaxy DSA process with dimension control of template pattern

Pattern decomposition for directed self assembly patterns templated by sidewall image transfer

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

Self-aligned inner-spacer replacement process using implantation

DSA grapho-epitaxy process with etch stop material

Bottom isolation for nanosheet transistors on bulk substrate

Alternating hardmasks for tight-pitch line formation

Techniques for VFET top source/drain epitaxy

Method and recording medium of reducing chemoepitaxy directed self-assembled defects

High-chi block copolymers for interconnect structures by directed self-assembly

Tone inverted directed self-assembly (DSA) fin patterning

Vertical field-effect-transistors having a silicon oxide layer with controlled thickness

Via formation using sidewall image transfer process to define lateral dimension

Alternating hardmasks for tight-pitch line formation

Efficient metal-insulator-metal capacitor

Graphoepitaxy directed self assembly

Via formation using sidewall image transfer process to define lateral dimension

Simultaneous photoresist development and neutral polymer layer formation

Non volatile resistive memory logic device

Via-to-metal tip connections in multi-layer chips

Source/drain extension regions and air spacers for nanosheet field-effect transistor structures

Self-aligned tunneling field effect transistors

Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch

Method and recording medium of reducing chemoepitaxy directed self-assembled defects

Techniques for vertical FET gate length control

Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch

Alternating hardmasks for tight-pitch line formation

Self-aligned single dummy fin cut with tight pitch

Self-aligned finFET formation

Embedded security circuit formed by directed self-assembly

Method and recording medium of reducing chemoepitaxy directed self-assembled defects

Self-aligned single dummy fin cut with tight pitch

Embedded security circuit formed by directed self-assembly

Pattern decomposition for directed self assembly patterns templated by sidewall image transfer

Graphoepitaxy directed self-assembly process for semiconductor fin formation

Alternating hardmasks for tight-pitch line formation

Undercut control in isotropic wet etch processes

Hybrid topographical and chemical pre-patterns for directed self-assembly of block copolymers

Graphoepitaxy directed self assembly

Litho-etch-litho-etch with self-aligned blocks

Hybrid topographical and chemical pre-patterns for directed self-assembly of block copolymers

Embedded chip identification formed by directed self-assembly

Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch

Nanosheet devices with improved electrostatic integrity

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

GUILLORN MICHAEL A

Tone inversion of self-assembled self-aligned structures

Tone inversion of self-assembled self-aligned structures

TESSERA INC

Alternating hardmasks for tight-pitch line formation

Efficient metal-insulator-metal capacitor

TESSERA LLC

Alternating hardmasks for tight-pitch line formation