Via-to-metal tip connections in multi-layer chips

Abstract

Integrated chips and methods for forming vias in the same include forming a multi-layer isolation structure on an underlying layer. The multi-layer isolation structure includes a first isolation layer around a second isolation layer. Conductive material is formed around the multi-layer isolation structure. The first isolation layer is etched back to expose at least a portion of a sidewall of the conductive material. A conductive via is formed to contact a top surface and the exposed portion of the sidewall of the conductive material.

What is claimed is: 
     
       1. A method of forming a via, comprising:
 etching a trench using a first photolithographic fabrication process with a minimum feature size; 
 forming a multi-layer isolation structure on an underlying layer, in the trench, the multi-layer isolation structure including a first isolation layer around a second isolation layer and having sloped sidewalls; 
 forming conductive material around the multi-layer isolation structure after forming the multi-layer isolation structure; 
 etching back the first isolation layer to expose at least a portion of a sidewall of the conductive material; and 
 forming a conductive via to contact a top surface and the exposed portion of the sidewall of the conductive material. 
 
     
     
       2. The method of  claim 1 , wherein the second isolation layer has a thickness sufficient to electrically isolate the conducive material on respective sides of the multi-layer isolation structure. 
     
     
       3. The method of  claim 1 , wherein the first isolation layer is formed from a first dielectric material and the second isolation layer is formed from a second dielectric material that is selectively etchable with respect to the first dielectric material. 
     
     
       4. The method of  claim 1 , furthering comprising forming a hardmask structure using a second fabrication process, wherein the hardmask structure has a dimension that is smaller than the minimum feature size of the first photolithographic fabrication process. 
     
     
       5. The method of  claim 4 , wherein the hardmask is positioned at least partially above the multi-layer isolation structure. 
     
     
       6. The method of  claim 1 , wherein the first isolation layer has a thickness of at least 8 nm. 
     
     
       7. The method of  claim 1 , wherein forming the multi-layer isolation structure comprises forming a plurality of such multi-layer isolation structures, with at least one region between the multi-layer isolation structures. 
     
     
       8. The method of  claim 7 , wherein forming the conductive material around the multi-layer isolation structures comprises forming a first conductive material with a cross-section with non-parallel sidewalls in at least one region between the multi-layer isolation structures and forming a second conductive material with a parallelogram cross-section in other regions. 
     
     
       9. A method of forming vias, comprising:
 etching trenches using a first photolithographic fabrication process with a minimum feature size; 
 forming a plurality of multi-layer isolation structures on an underlying layer, in the trenches, each including a first isolation layer around a second isolation layer and having sloped sidewalls; 
 forming conductive material around and between the multi-layer isolation structures, after forming the plurality of multi-layer isolation structures, with conductive material between the multi-layer isolation structures having a cross-section with non-parallel sidewalls and conductive material in other regions having a parallelogram cross-section; 
 etching back the first isolation layer to expose at least a portion of a sidewall of the conductive material; and 
 forming a conductive via to contact a top surface and the exposed portion of the sidewall of the conductive material. 
 
     
     
       10. The method of  claim 9 , wherein the second isolation layer has a thickness sufficient to electrically isolate the conducive material on respective sides of the multi-layer isolation structure. 
     
     
       11. The method of  claim 9 , wherein the first isolation layer is formed from a first dielectric material and the second isolation layer is formed from a second dielectric material that is selectively etchable with respect to the first dielectric material. 
     
     
       12. The method of  claim 9 , furthering comprising forming a hardmask structure using a second fabrication process, wherein the hardmask structure has a dimension that is smaller than the minimum feature size of the first photolithographic fabrication process. 
     
     
       13. The method of  claim 12 , wherein the hardmask is positioned at least partially above the multi-layer isolation structure. 
     
     
       14. The method of  claim 9 , wherein the first isolation layer has a thickness of at least 8 nm.