Inventor
LERNER RALF
DE29 patents
⚠️ This page may combine multiple inventors who share the name “LERNER RALF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LERNER RALF
9 patentsUS8278183B2Oct 2, 2012
Production of isolation trenches with different sidewall dopings
LERNER RALF32 citations91
US8823095B2Sep 2, 2014
MOS-power transistors with edge termination with small area requirement
LERNER RALF5 citations72
US8247884B2Aug 21, 2012
Semiconductor structure for fabricating a handle wafer contact in a trench insulated SOI disc
LERNER RALF2 citations61
US9070768B2Jun 30, 2015
DMOS transistor having an increased breakdown voltage and method for production
LERNER RALF2 citations51
US8530999B2Sep 10, 2013
Semiconductor component with isolation trench intersections
LERNER RALF0 citations50
US8793116B2Jul 29, 2014
Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
LERNER RALF0 citations45
US8190415B2May 29, 2012
Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
LERNER RALF0 citations45
US8921945B2Dec 30, 2014
High-voltage power transistor using SOI technology
LERNER RALF0 citations40
US8448101B2May 21, 2013
Layout method for vertical power transistors having a variable channel width
LERNER RALF0 citations35
X FAB SEMICONDUCTOR FOUNDRIES
9 patentsUS7588948B2Sep 15, 2009
Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods
X FAB SEMICONDUCTOR FOUNDRIES7 citations73
US10186502B1Jan 22, 2019
Integrated circuit having a component provided by transfer print and method for making the integrated circuit
X FAB SEMICONDUCTOR FOUNDRIES2 citations72
US8053897B2Nov 8, 2011
Production of a carrier wafer contact in trench insulated integrated SOI circuits having high-voltage components
X FAB SEMICONDUCTOR FOUNDRIES4 citations62
US7598098B2Oct 6, 2009
Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material
X FAB SEMICONDUCTOR FOUNDRIES6 citations62
US7625805B2Dec 1, 2009
Passivation of deep isolating separating trenches with sunk covering layers
X FAB SEMICONDUCTOR FOUNDRIES4 citations60
US7271074B2Sep 18, 2007
Trench insulation in substrate disks comprising logic semiconductors and power semiconductors
X FAB SEMICONDUCTOR FOUNDRIES6 citations60
US7989921B2Aug 2, 2011
Soi vertical bipolar power component
X FAB SEMICONDUCTOR FOUNDRIES0 citations41
US7517813B2Apr 14, 2009
Two-step oxidation process for semiconductor wafers
X FAB SEMICONDUCTOR FOUNDRIES0 citations39
US7989308B2Aug 2, 2011
Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher voltages
X FAB SEMICONDUCTOR FOUNDRIES0 citations33
X FAB SEMICONDUCTOR FOUNDRIES GMBH
7 patentsUS11916104B2Feb 27, 2024
Trench insulation structure with enlarged electrically conductive side wall
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations62
US11829074B2Nov 28, 2023
Geometrically shaped components in an assembly for a transfer print and associated methods
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations62
US11355582B2Jun 7, 2022
Trench insulation structure with enlarged electrically conductive side wall
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations62
US10930497B2Feb 23, 2021
Semiconductor substrate and method for producing a semiconductor substrate
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations62
US11437266B2Sep 6, 2022
Method of manufacturing semiconductor devices to increase yield in micro-transfer printing
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations51
US10845710B2Nov 24, 2020
Geometrically shaped components in an assembly for a transfer print and associated methods
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations51
US11037812B2Jun 15, 2021
Method for a transfer print between substrates
X FAB SEMICONDUCTOR FOUNDRIES GMBH0 citations41
KITTLER GABRIEL
2 patentsUS8759169B2Jun 24, 2014
Method for producing silicon semiconductor wafers comprising a layer for integrating III-V semiconductor components
KITTLER GABRIEL8 citations79
US8546207B2Oct 1, 2013
Method for fabricating semiconductor wafers for the integration of silicon components with HEMTs, and appropriate semiconductor layer arrangement
KITTLER GABRIEL3 citations57