Method for fabricating semiconductor wafers for the integration of silicon components with HEMTs, and appropriate semiconductor layer arrangement

Abstract

The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers ( 24 ) of the HEMT design ( 2 ) placed on it stretching over two mutually insulated regions ( 24 a, 24 b ) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

We claim: 
     
       1. A method for fabricating a semiconductor wafer comprising an active silicon layer and having a structure of group III-V layers for the integration of silicon components comprising high electron mobility transistors using the structure of group III-V layers, the method comprising the steps of:
 providing a substrate wafer whereon the active silicon layer, the active silicon layer comprising a first region and a second region, and having an isolation trench positioned therebetween to electrically insulate the first and second regions; 
 fabricating a patterned layer stack having an intermediate layer for lattice parameter adaptation and positioned on the active silicon layer over at least a part of the first region, the isolation trench, and at least a part of the second region; a III-V semiconductor layer positioned above the intermediate layer; and a III x III 1-x -V semiconductor layer positioned above the III-V semiconductor layer; 
 forming an electrode over a part of the III x III 1-x -V semiconductor layer; wherein the substrate wafer comprises a buried insulation layer on which the active silicon layer is formed, such that the first and second regions are delimited by the buried insulation layer and the isolation trench. 
 
     
     
       2. The method according to  claim 1 , wherein the active silicon layer is fabricated so that a region of said active layer is laterally isolated by a region of an insulation of the isolation trench, in which region at least one of the silicon components is fabricated. 
     
     
       3. The method according to  claim 1 , wherein the III x III 1-x -V semiconductor layer comprises aluminum, gallium and nitrogen, and the III-V semiconductor layer is a GaN layer. 
     
     
       4. The method according to  claim 1 , wherein the isolation trench is a shallow isolation trench. 
     
     
       5. The method according to  claim 1 , further comprising:
 fabricating a source region and a drain region, the source region positioned over the first region of the active silicon layer and the drain region positioned over the second region of the active silicon layer. 
 
     
     
       6. The method according to  claim 5 , wherein the electrode is formed as a gate and is positioned over the first region of the active silicon layer.