Inventor

PANDEY SHESH MANI

US71 patents

⚠️ This page may combine multiple inventors who share the name “PANDEY SHESH MANI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANDEY SHESH MANI

GLOBALFOUNDRIES US INC

Photonics structures having a locally-thickened dielectric layer

Split gate (SG) memory device and novel methods of making the SG-memory device

Bipolar transistor and gate structure on semiconductor fin and methods to form same

Bipolar transistors

Lateral bipolar junction transistors with an airgap spacer

Heterojunction bipolar transistors

Heterojunction bipolar transistors

Transistor comprising an air gap positioned adjacent a gate electrode

Metal oxide semiconductor devices and integration methods

Metal oxide semiconductor devices and methods of making thereof

Enlarged multilayer nitride waveguide for photonic integrated circuit

Bipolar transistor structure with base protruding from emitter/collector and methods to form same

Vertical bipolar transistors

Bipolar junction transistors including a portion of a base layer inside a cavity in a dielectric layer

Multiple-core heterogeneous waveguide structures including multiple slots

Bipolar junction transistors with duplicated terminals

Concurrent manufacture of field effect transistors and bipolar junction transistors with gain tuning

Semiconductor devices with uniform gate height and method of forming same

N-well resistor

Optical waveguide with stacked cladding material layers

Waveguide cores surrounded by an airgap

Semiconductor-on-insulator field-effect transistors including stress-inducing components

Bipolar junction transistors with a base layer participating in a diode

Silicon-controlled rectifiers in a silicon-on-insulator technology

Lateral bipolar junction transistors with a back-gate

Lateral bipolar transistor with emitter and collector regions including portions within In-insulator layer cavities and method

Epi semiconductor structures with increased epi volume in source/drain regions of a transistor device formed on an SOI substrate

Epi semiconductor material structures in source/drain regions of a transistor device formed on an SOI substrate

GLOBALFOUNDRIES INC

Fabricating fin-type field effect transistor with punch-through stop region

Transistor fins with different thickness gate dielectric

Vertical transistor structure with looped channel

Chip integration including vertical field-effect transistors and bipolar junction transistors

Sub-fin doping method

Device with diffusion blocking layer in source/drain region

Device with diffusion blocking layer in source/drain region

Shaped gate caps in dielectric-lined openings

Hybrid fin cut with improved fin profiles

Field-effect transistors with fins formed by a damascene-like process

Methods for fin thinning providing improved SCE and S/D EPI growth

Multiple-step epitaxial growth S/D regions for NMOS FinFET

Low resistance conductive contacts

Source/drain profile engineering for enhanced p-MOSFET

FinFET conformal junction and high EPI surface dopant concentration method and device

Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same

Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication

Fin-FET replacement metal gate structure and method of manufacturing the same

Semiconductor device with reduced parasitic capacitance

Using source/drain contact cap during gate cut

Methods of forming source/drain regions on FinFET devices

YEONG SAI HOOI

Method for fabricating semiconductor devices using stress engineering