Lateral bipolar transistor with emitter and collector regions including portions within In-insulator layer cavities and method

Abstract

A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.

What is claimed is: 
     
       1. A structure comprising:
 an insulator layer, 
 a semiconductor layer on the insulator layer; 
 an emitter region comprising: an emitter portion of the semiconductor layer; and an emitter semiconductor layer within an emitter cavity in the insulator layer and adjacent to the emitter portion, the emitter semiconductor layer comprising an upper portion over a top surface of the emitter portion of the semiconductor layer; 
 a collector region comprising: a collector portion of the semiconductor layer; and a collector semiconductor layer within a collector cavity in the insulator layer and adjacent to the collector portion, the collector semiconductor layer comprising an upper portion over a top surface of the collector portion of the semiconductor layer; and 
 a base region positioned laterally between the emitter region and the collector region wherein the emitter cavity and the collector cavity each extend laterally partially below the base region. 
 
     
     
       2. The structure of  claim 1 ,
 wherein the emitter semiconductor layer fills an emitter opening that extends through the emitter portion to the emitter cavity, and 
 wherein the collector semiconductor layer fills a collector opening that extends through the collector portion to the collector cavity. 
 
     
     
       3. The structure of  claim 1 ,
 wherein the emitter semiconductor layer completely fills the emitter cavity, and 
 wherein the collector semiconductor layer completely fills the collector cavity. 
 
     
     
       4. The structure of  claim 1 , further comprising a collector extension layer between the collector portion and the collector semiconductor layer. 
     
     
       5. The structure of  claim 1 , wherein the base region comprises:
 a base portion of the semiconductor layer positioned laterally between the emitter portion and the collector portion; and 
 a base stack on the base portion and comprising at least one base semiconductor layer. 
 
     
     
       6. The structure of  claim 5 , further comprising dielectric sidewall spacers positioned laterally adjacent to opposing sidewalls of the base stack. 
     
     
       7. The structure of  claim 5 ,
 wherein the base portion is thinner than the emitter portion and the collector portion, and 
 wherein the base stack comprises:
 a base semiconductor layer on the base portion; and 
 an additional base semiconductor layer on the base semiconductor layer. 
 
 
     
     
       8. The structure of  claim 7 ,
 wherein the base semiconductor layer comprises a monocrystalline semiconductor layer, and 
 wherein the additional base semiconductor layer comprises a polycrystalline semiconductor layer. 
 
     
     
       9. The structure of  claim 7 , wherein base semiconductor layer and the additional base semiconductor layer comprise different semiconductor materials. 
     
     
       10. The structure of  claim 7 , wherein the base semiconductor layer comprises silicon germanium and wherein the additional base semiconductor layer comprises silicon. 
     
     
       11. The structure of  claim 7 ,
 wherein the additional base semiconductor layer has a first-type conductivity, 
 wherein the emitter region and the collector region have a second-type conductivity, and 
 wherein base semiconductor layer is any of undoped and doped so as to have the first- type conductivity at a lower conductivity level than the additional base semiconductor layer. 
 
     
     
       12. A structure comprising:
 an insulator layer, 
 a semiconductor layer on the insulator layer; 
 an emitter region comprising: an emitter portion of the semiconductor layer; and an emitter semiconductor layer partially filling an emitter cavity in the insulator layer and adjacent to the emitter portion, the emitter semiconductor layer comprising an upper portion over a top surface of the emitter portion of the semiconductor layer; 
 a collector region comprising: a collector portion of the semiconductor layer; and a collector semiconductor layer partially filling a collector cavity in the insulator layer and adjacent to the collector portion, the collector semiconductor layer comprising an upper portion over a top surface of the collector portion of the semiconductor layer; and 
 a base region positioned laterally between the emitter region and the collector region wherein the emitter cavity and the collector cavity each extend laterally partially below the base region. 
 
     
     
       13. A method comprising:
 forming a base region; and 
 forming an emitter region and a collector region, 
 wherein the base region is positioned laterally between the emitter region and the collector region, 
 wherein the emitter region comprises: an emitter portion of a semiconductor layer on an insulator layer; and an emitter semiconductor layer within an emitter cavity in the insulator layer and immediately adjacent to the emitter portion, the emitter semiconductor layer comprising an upper portion over a top surface of the emitter portion of the semiconductor layer, 
 wherein the collector region comprising: a collector portion of the semiconductor layer; and a collector semiconductor layer within a collector cavity in the insulator layer and immediately adjacent to the collector portion, the collector semiconductor layer comprising an upper portion over a top surface of the collector portion of the semiconductor layer, and 
 wherein the emitter cavity and the collector cavity each extend laterally partially below the base region. 
 
     
     
       14. The method of  claim 13 , wherein the forming of the emitter region and the collector region comprises:
 forming an emitter opening through the emitter portion to the insulator layer and a collector opening through the collector portion to the insulator layer; 
 forming the emitter cavity and the collector cavity; and 
 performing an epitaxial deposition process so that the emitter semiconductor layer at least partially fills the emitter cavity, fills the emitter opening and further extends onto the top surface of the emitter portion and so that the collector semiconductor layer at least partially fills the collector cavity, fills the collector opening and further extends onto the top surface of the collector portion. 
 
     
     
       15. The method of  claim 14 ,
 wherein the emitter semiconductor layer completely fills the emitter cavity, and 
 wherein the collector semiconductor layer completely fills the collector cavity. 
 
     
     
       16. The method of  claim 14 ,
 wherein the emitter semiconductor layer only partially fills the emitter cavity, 
 wherein the collector semiconductor layer only partially fills the collector cavity, and 
 wherein the emitter cavity and the collector cavity each further include a pocket of air, of gas, or under vacuum. 
 
     
     
       17. The method of  claim 14 , wherein the forming of the base region comprises:
 recessing a base portion of the semiconductor layer, wherein the base portion is positioned laterally between the emitter portion and the collector portion; and 
 forming a base stack on the base portion; and 
 forming dielectric sidewall spacers positioned laterally adjacent to opposing sidewalls of the base stack. 
 
     
     
       18. The method of  claim 17 , wherein the forming of the base stack comprises:
 forming a base semiconductor layer on the base portion, wherein the base semiconductor layer comprises a monocrystalline semiconductor layer; and 
 forming an additional base semiconductor layer on the base semiconductor layer, wherein the additional base semiconductor layer comprises a polycrystalline semiconductor layer. 
 
     
     
       19. The method of  claim 18 , wherein base semiconductor layer and the additional base semiconductor layer comprise different semiconductor materials. 
     
     
       20. The method of  claim 19 ,
 wherein the additional base semiconductor layer has a first-type conductivity, 
 wherein the emitter region and the collector region have a second-type conductivity, and 
 wherein base semiconductor layer is any of undoped and doped so as to have the first-type conductivity at a lower conductivity level than the additional base semiconductor layer.