Inventor

SCHULTZ RICHARD T

US58 patents

⚠️ This page may combine multiple inventors who share the name “SCHULTZ RICHARD T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHULTZ RICHARD T

ADVANCED MICRO DEVICES INC

Gate all around device architecture with local oxide

Standard cell and power grid architectures with EUV lithography

Metal zero contact via redundancy on output nodes and inset power rail architecture

Vertical gate all around library architecture

Trench silicide and gate open with local interconnect with replacement gate process

Cross field effect transistor library cell architecture design

Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level

Gate contact over active region in cell

Sinusoidal shaped capacitor architecture in oxide

Oscillating capacitor architecture in polysilicon for improved capacitance

Double spacer immersion lithography triple patterning flow and method

Gate all around device architecture with hybrid wafer bond technique

Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level

Cross field effect transistors (XFETs) in integrated circuits

Cross FET SRAM cell layout

Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells

Cross field effect transistor (XFET) library architecture power routing

Cross FET SRAM cell layout

Gate contact over active region in cell

Standard cell layout architectures and drawing styles for 5nm and beyond

Backside power delivery and power grid pattern to support 3D die stacking

Dual-track bitline scheme for 6T SRAM cells

Folded cell layout for 6T SRAM cell

LSI LOGIC CORP

Floor plan development electromigration and voltage drop analysis tool

Floor plan-based power bus analysis and design tool for integrated circuits

Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times

Process, voltage and temperature independent clock tree deskew circuitry-active drive method

Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method

Dynamically minimizing clock tree skew in an integrated circuit

Radially-increasing core power bus grid architecture

Metastability risk simulation analysis tool and method

Power redistribution bus for a wire bonded integrated circuit

Static timing and risk analysis tool

Thick traces from multiple damascene layers

Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times

Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method

Load sensing, slew rate shaping, output signal pad cell driver circuit and method

Integrated circuit having radially varying power bus grid architecture

Meta-hardened flip-flop

Reliability circuit for applying an AC stress signal or DC measurement to a transistor device

SCHULTZ RICHARD T

Trench silicide and gate open with local interconnect with replacement gate process

Process for forming fins for a FinFET device

Selective local interconnect to gate in a self aligned local interconnect process

Self-aligned trench contact and local interconnect with replacement gate process

SRAM bit cell with self-aligned bidirectional local interconnects

GLOBALFOUNDRIES INC

Methods for fabricating FinFET structures having different channel lengths

Methods for fabricating FinFET structures having different channel lengths

LSI CORP

Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit

N cell height decoupling circuit

LS1 CORP

Instantaneous voltage drop sensitivity analysis tool (IVDSAT)