Thick traces from multiple damascene layers

Abstract

Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

What is claimed is:  
     
       1. A capacitor in an integrated circuit comprising: 
       a first signal trace and a second signal trace fabricated in at least one signal layer, said signal layer having a first dielectric material;  
       at least two electrodes, each electrode being formed in a plurality of successive electrode layers comprising a second dielectric material;  
       said electrodes being comprised of conductors formed in said successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers; and  
       wherein said first signal trace and said second signal trace are connected to alternating electrodes.  
     
     
       2. The capacitor of  claim 1  further comprising: 
       wherein said first dielectric material being selected to minimize capacitive coupling between said signal traces; and  
       wherein said second dielectric material being selected to maximize capacitive coupling between said signal traces.  
     
     
       3. The capacitor of  claim 1  wherein said first dielectric material and said second dielectric material are the same dielectric material. 
     
     
       4. An inductor in an integrated circuit comprising: 
       successive layers comprising a top layer, at least one intermediate layer, and a bottom layer;  
       said intermediate layer comprising a plurality of concentric loops, each loop being disunited at two points substantially opposite each other;  
       said loops being comprised of conductors formed in said successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers; and  
       said top layer further comprising at least one trace connecting at least two of said concentric loops.  
     
     
       5. An inductor in an integrated circuit comprising: 
       a coiled trace formed in a plurality of successive layers, said coiled trace being comprised of conductors in successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers, said layers further comprising a first non-conductive material, said coiled trace having a first end and a second end;  
       a first signal trace and a second signal trace in a signal layer, said signal layer comprising a second non-conductive material;  
       said first signal trace being in electrical communication with said first end of said coiled trace; and  
       said second signal trace being in electrical communication with said second end of said coiled trace.