Inventor

GIOVANNINI THOMAS J

US49 patents

⚠️ This page may combine multiple inventors who share the name “GIOVANNINI THOMAS J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GIOVANNINI THOMAS J

RAMBUS INC

Memory module register access

Method and apparatus for calibrating write timing in a memory system

Memory capacity expansion using a memory riser

Data-buffer component with variable-width data ranks and configurable data-rank timing

Memory module with emulated memory device population

Memory modules and systems with variable-width data ranks and configurable data-rank timing

Method and apparatus for calibrating write timing in a memory system

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Extended capacity memory module with dynamic data buffers

Extended capacity memory module with dynamic data buffers

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

High-performance, high-capacity memory systems and modules

Memory module register access

Protocol including a command-specified timing reference signal

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Method and apparatus for calibrating write timing in a memory system

Memories and memory components with interconnected and redundant data interfaces

Memory controller that uses a specific timing reference signal in connection with a data burst following a specified idle period

Signal receiver with skew-tolerant strobe gating

Signal receiver with skew-tolerant strobe gating

Burst-tolerant decision feedback equalization

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Protocol including selective output by memory of a timing reference signal

High-performance, high-capacity memory systems and modules

Method and apparatus for calibrating write timing in a memory system

Protocol including a command-specified timing reference signal

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Method and apparatus for calibrating write timing in a memory system

Burst-tolerant decision feedback equalization

Memory module register access

Memory modules and systems with variable-width data ranks and configurable data-rank timing

Signal receiver with skew-tolerant strobe gating

Memory module register access

Burst-tolerant decision feedback equalization

Memory module and registered clock driver with configurable data-rank timing

Memories and memory components with interconnected and redundant data interfaces

Burst-tolerant decision feedback equalization

Memory module register access

Circuits and methods for self-adaptive decision-feedback equalization in a memory system

GIOVANNINI THOMAS J

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Sharing a check bit memory device between groups of memory devices

SHAEFFER IAN

Protocol including a command-specified timing reference signal

INTEL CORP

Optical receiver protection circuit