Signal receiver with skew-tolerant strobe gating

Abstract

A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

What is claimed is: 
     
       1. An integrated-circuit component comprising:
 a signaling interface to receive (i) a timing strobe signal, and (ii) first and second commands indicating that first and second data bursts are to be sampled in response to respective first and second sets of active edges within the timing strobe signal, the timing strobe signal including inactive edges at least prior to the first set of active edges and after the second set of active edges; 
 a first-in-first-out (FIFO) storage structure; and 
 control circuitry to:
 progressively load qualification values corresponding to the active edges within the first and second sets of active edges into the FIFO storage structure; and 
 generate, based at least in part on the qualification values loaded into the FIFO storage structure, a gated version of the timing strobe signal that lacks the inactive edges. 
 
 
     
     
       2. The integrated-circuit component of  claim 1  wherein the control circuitry comprises reset circuitry to selectively reset the qualification values within the FIFO storage structure to a predetermined state after loading the qualification values corresponding to the active edges within the first set of active edges into the FIFO storage structure and prior to loading the qualification values corresponding to the active edges within the second set of active edges into the FIFO storage structure. 
     
     
       3. The integrated-circuit component of  claim 2  wherein the reset circuitry to selectively reset the qualification values within the FIFO storage structure to the predetermined state comprises circuitry to reset the qualification values within the FIFO storage structure to the predetermined state if an elapsed time between receipt of the first command and receipt of the second command is less than a predetermined time interval. 
     
     
       4. The integrated-circuit component of  claim 3  wherein the circuitry to reset the qualification values within the FIFO storage structure to the predetermined state if the elapsed time between receipt of the first command and receipt of the second command is less than the predetermined time interval comprises circuitry to (i) generate a first value indicative of the elapsed time between receipt of the first command and receipt of the second command and (ii) compare the first value with a threshold value corresponding to the predetermined time interval. 
     
     
       5. The integrated-circuit component of  claim 3  wherein the reset circuitry to selectively reset the qualification values within the FIFO storage structure to the predetermined state comprises circuitry to refrain from resetting the qualification values within the FIFO storage structure to the predetermined state if the elapsed time between receipt of the first command and receipt of the second command exceeds the predetermined time interval. 
     
     
       6. The integrated-circuit component of  claim 5  wherein the control circuitry to progressively load qualification values into the FIFO storage structure comprises circuitry to sequentially shift the qualification values into the FIFO storage structure such that, by refraining from resetting the qualification values within the FIFO storage structure, and thereafter shifting at least one of the qualification values corresponding to the active edges within the second set of active edges into the FIFO storage structure, the FIFO storage structure simultaneously contains one or more qualification values corresponding to the active edges within the first set of active edges and one or more qualification values corresponding to the active edges within the second set of active edges. 
     
     
       7. The integrated-circuit component of  claim 1  wherein the control circuitry to progressively load qualification values into the FIFO storage structure comprises circuitry to sequentially shift the qualification values into the FIFO storage structure in response to transitions of a reference clock signal. 
     
     
       8. The integrated-circuit component of  claim 7  wherein the reference clock signal exhibits a time-varying phase offset relative to the timing strobe signal. 
     
     
       9. The integrated-circuit component of  claim 8  wherein the signaling interface to receive the first and second commands comprises circuitry to sample the first command at times indicated by one or more transitions of the reference clock signal and then sample the second command at times indicated by one or more later transitions of the reference clock signal. 
     
     
       10. The integrated-circuit component of  claim 1  wherein the gated version of the timing strobe signal includes the first and second sets of active edges, the integrated-circuit component further comprising:
 a core memory array; and 
 data circuitry to:
 sample the first write data burst in response to the first command and at times indicated by the first set of active edges within the gated version of the timing strobe signal to generate a first set of write data values; 
 store the first set of write data values within the core memory array; 
 sample the second write data burst in response to the second command and at times indicated by the second set of active edges within the gated version of the timing strobe signal to generate a second set of write data values; and 
 store the second set of write data values within the core memory array. 
 
 
     
     
       11. A method of operation within an integrated-circuit component, the method comprising:
 receiving first and second commands indicating that first and second data bursts are to be sampled in response to respective first and second sets of active edges within a timing strobe signal, the timing strobe signal including inactive edges at least prior to the first set of active edges and after the second set of active edges; 
 progressively loading qualification values corresponding to the active edges within the first and second sets of active edges into a first-in-first-out (FIFO) storage structure; and 
 generating, based at least in part on the qualification values, a gated version of the timing strobe signal that lacks the inactive edges. 
 
     
     
       12. The method of  claim 11  further comprising, after loading qualification values corresponding to the active edges within the first set of active edges into the FIFO storage structure and prior to loading qualification values corresponding to the active edges within the second set of active edges into the FIFO storage structure, selectively resetting the qualification values within the FIFO storage structure to a predetermined state. 
     
     
       13. The method of  claim 12  wherein selectively resetting the qualification values within the FIFO storage structure to the predetermined state comprises resetting the qualification values within the FIFO storage structure to the predetermined state if an elapsed time between receipt of the first command and receipt of the second command is less than a predetermined time interval. 
     
     
       14. The method of  claim 13  further comprising generating a first value indicative of the elapsed time between receipt of the first command and receipt of the second command and comparing the first value with a threshold value corresponding to the predetermined time interval. 
     
     
       15. The method of  claim 13  wherein selectively resetting the qualification values within the FIFO storage structure to the predetermined state comprises refraining from resetting the qualification values within the FIFO storage structure to the predetermined state if the elapsed time between receipt of the first command and receipt of the second command exceeds the predetermined time interval. 
     
     
       16. The method of  claim 15  wherein progressively loading qualification values into the FIFO storage structure comprises sequentially shifting the qualification values into the FIFO storage structure such that, by refraining from resetting the qualification values within the FIFO storage structure, and thereafter shifting at least one of the qualification values corresponding to the active edges within the second set of active edges into the FIFO storage structure, the FIFO storage structure simultaneously contains one or more qualification values corresponding to the active edges within the first set of active edges and one or more qualification values corresponding to the active edges within the second set of active edges. 
     
     
       17. The method of  claim 11  wherein progressively loading qualification values into the FIFO storage structure comprises sequentially shifting the qualification values into the FIFO storage structure in response to transitions of a reference clock signal. 
     
     
       18. The method of  claim 17  wherein the reference clock signal exhibits a time-varying phase offset relative to the timing strobe signal. 
     
     
       19. The method of  claim 18  wherein receiving the first and second commands comprises sampling the first command at times indicated by one or more transitions of the reference clock signal and then sampling the second command at times indicated by one or more later transitions of the reference clock signal. 
     
     
       20. The method of  claim 11  wherein the gated version of the timing strobe signal includes the first and second sets of active edges, the method further comprising:
 sampling the first write data burst in response to the first command and at times indicated by the first set of active edges within the gated version of the timing strobe signal to generate a first set of write data values; 
 storing the first set of write data values within a core memory array of the integrated-circuit component; 
 sampling the second write data burst in response to the second command and at times indicated by the second set of active edges within the gated version of the timing strobe signal to generate a second set of write data values; and 
 storing the second set of write data values within the core memory array. 
 
     
     
       21. An integrated-circuit component comprising:
 means for receiving a timing strobe signal; 
 means for receiving first and second commands indicating that first and second data bursts are to be sampled in response to respective first and second sets of active edges within the timing strobe signal, the timing strobe signal including inactive edges at least prior to the first set of active edges and after the second set of active edges; 
 a first-in-first-out (FIFO) storage structure; 
 means for progressively loading qualification values corresponding to the active edges within the first and second sets of active edges into the FIFO storage structure; and 
 means for generating, based at least in part on the qualification values loaded into the FIFO storage structure, a gated version of the timing strobe signal that lacks the inactive edges.