Inventor · disambiguated record
Thomas J. Giovannini
Also filed as: GIOVANNINI THOMAS · GIOVANNINI THOMAS J
64 granted patents·9 pending applications·308 citations·filing 2005–2025
98Inventor score
Top patents by PatentIndex Score
73 records- 0198US10146608B2Memory module register accessRAMBUS INC·Filed 2016·Granted Dec 4, 2018·36 cites·16 claims
- 0297US9881662B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2017·Granted Jan 30, 2018·16 cites·19 claims
- 0396US11809345B2Data-buffer component with variable-width data ranks and configurable data-rank timingRAMBUS INC·Filed 2022·Granted Nov 7, 2023·4 cites·20 claims
- 0496US11755508B2High-performance, high-capacity memory systems and modulesRAMBUS INC·Filed 2021·Granted Sep 12, 2023·3 cites·12 claims
- 0596US11294830B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2020·Granted Apr 5, 2022·8 cites·18 claims
- 0696US7729621B2Controlling a bias voltage for a Mach-Zehnder modulatorINTEL CORP·Filed 2007·Granted Jun 1, 2010·68 cites·18 claims
- 0795US8407441B2Method and apparatus for calibrating write timing in a memory systemGIOVANNINI THOMAS J·Filed 2011·Granted Mar 26, 2013·18 cites·22 claims
- 0894US11127444B1Signal receiver with skew-tolerant strobe gatingRAMBUS INC·Filed 2020·Granted Sep 21, 2021·3 cites·21 claims
- 0994US9298228B1Memory capacity expansion using a memory riserRAMBUS INC·Filed 2015·Granted Mar 29, 2016·28 cites·17 claims
- 1093US10789185B2Memory modules and systems with variable-width data ranks and configurable data-rank timingRAMBUS INC·Filed 2017·Granted Sep 29, 2020·8 cites·9 claims
- 1192US10223309B2Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modulesRAMBUS INC·Filed 2015·Granted Mar 5, 2019·8 cites·21 claims
- 1292US9142281B1Method and apparatus for calibrating write timing in a memory systemGIOVANNINI THOMAS J·Filed 2015·Granted Sep 22, 2015·6 cites·20 claims
- 1391US10304517B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2018·Granted May 28, 2019·5 cites·20 claims
- 1490US11068161B1Memory module with emulated memory device populationRAMBUS INC·Filed 2017·Granted Jul 20, 2021·11 cites·21 claims
- 1590US9916873B2Extended capacity memory module with dynamic data buffersRAMBUS INC·Filed 2016·Granted Mar 13, 2018·9 cites·19 claims
- 1688US10613995B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2016·Granted Apr 7, 2020·7 cites·18 claims
- 1788US2025111873A1Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2024·Application pending·0 cites
- 1887US11768780B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2022·Granted Sep 26, 2023·1 cites·20 claims
- 1987US10360972B2Memories and memory components with interconnected and redundant data interfacesRAMBUS INC·Filed 2016·Granted Jul 23, 2019·4 cites·13 claims
- 2086US11573849B2Memory module register accessRAMBUS INC·Filed 2021·Granted Feb 7, 2023·1 cites·20 claims
- 2186US10109324B2Extended capacity memory module with dynamic data buffersRAMBUS INC·Filed 2018·Granted Oct 23, 2018·6 cites·20 claims
- 2285US9412428B2Memory components and controllers that calibrate multiphase synchronous timing referencesGIOVANNINI THOMAS·Filed 2012·Granted Aug 9, 2016·9 cites·20 claims
- 2385US9263103B2Method and apparatus for calibrating write timing in a memory systemGIOVANNINI THOMAS J·Filed 2008·Granted Feb 16, 2016·8 cites·15 claims
- 2485US9177632B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2015·Granted Nov 3, 2015·2 cites·20 claims
- 2585US2025181531A1Memory Modules and Systems with Variable-Width Data Ranks and Configurable Data-Rank TimingRAMBUS INC·Filed 2024·Application pending·0 cites
- 2684US11763865B1Signal receiver with skew-tolerant strobe gatingRAMBUS INC·Filed 2021·Granted Sep 19, 2023·1 cites·21 claims
- 2784US10169258B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2016·Granted Jan 1, 2019·3 cites·17 claims
- 2883US12436907B2Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modulesRAMBUS INC·Filed 2023·Granted Oct 7, 2025·0 cites·20 claims
- 2983US9552865B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2015·Granted Jan 24, 2017·3 cites·20 claims
- 3082US12298842B2Memory module register accessRAMBUS INC·Filed 2024·Granted May 13, 2025·0 cites·20 claims
- 3182US12136452B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 3282US10320591B2Burst-tolerant decision feedback equalizationRAMBUS INC·Filed 2016·Granted Jun 11, 2019·3 cites·23 claims
- 3382US9824730B2Memory components and controllers that calibrate multiphase synchronous timing referencesRAMBUS INC·Filed 2016·Granted Nov 21, 2017·4 cites·20 claims
- 3482US9665507B2Protocol including a command-specified timing reference signalSHAEFFER IAN·Filed 2011·Granted May 30, 2017·5 cites·33 claims
- 3581US12210467B2Memory modules and systems with variable-width data ranks and configurable data-rank timingRAMBUS INC·Filed 2023·Granted Jan 28, 2025·0 cites·19 claims
- 3681US2025110897A1Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2024·Application pending·0 cites
- 3780US12386763B2Protocol including selective output by memory of a timing reference signalRAMBUS INC·Filed 2023·Granted Aug 12, 2025·0 cites·20 claims
- 3879US12463849B2Burst-tolerant decision feedback equalizationRAMBUS INC·Filed 2024·Granted Nov 4, 2025·0 cites·20 claims
- 3979US11953981B2Memory module register accessRAMBUS INC·Filed 2023·Granted Apr 9, 2024·0 cites·20 claims
- 4079US11682448B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2022·Granted Jun 20, 2023·0 cites·20 claims
- 4179US9141472B2Sharing a check bit memory device between groups of memory devicesGIOVANNINI THOMAS J·Filed 2012·Granted Sep 22, 2015·5 cites·34 claims
- 4279US2024428835A1Signal receiver with skew-tolerant strobe gatingRAMBUS INC·Filed 2024·Application pending·0 cites
- 4378US12298926B2High-performance, high-capacity memory systems and modulesRAMBUS INC·Filed 2023·Granted May 13, 2025·0 cites·17 claims
- 4478US12141081B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2023·Granted Nov 12, 2024·0 cites·20 claims
- 4578US12062413B1Signal receiver with skew-tolerant strobe gatingRAMBUS INC·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
- 4677US11907139B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2022·Granted Feb 20, 2024·0 cites·18 claims
- 4777US11815940B2Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modulesRAMBUS INC·Filed 2022·Granted Nov 14, 2023·0 cites·20 claims
- 4877US2025328457A1Circuits and methods for self-adaptive decision-feedback equalization in a memory systemRAMBUS INC·Filed 2025·Application pending·0 cites
- 4976US10607685B2Method and apparatus for calibrating write timing in a memory systemRAMBUS INC·Filed 2019·Granted Mar 31, 2020·1 cites·20 claims
- 5076US9389637B2Methods and systems for recovering intermittent timing-reference signalsRAMBUS INC·Filed 2013·Granted Jul 12, 2016·4 cites·32 claims
Showing the top 50 of 73 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →