Inventor

PLONDKE ERICH JAMES

US35 patents

⚠️ This page may combine multiple inventors who share the name “PLONDKE ERICH JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PLONDKE ERICH JAMES

QUALCOMM INC

Systems and methods of using a hypervisor with guest operating systems and virtual processors

Hardware-based stack control information protection

Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systems

Externally programmable memory management unit

Systems and methods of executing multiple hypervisors using multiple sets of processors

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Dedicated arithmetic encoding instruction

Shared interrupt controller for a multi-threaded processor

Parity for instruction packets

Systems and methods for cache line replacement

Selective translation lookaside buffer search and page fault

System and method of determining an address of an element within a table

Using the least significant bits of a called function&#39;s address to switch processor modes

Adaptive mode translation lookaside buffer search and access fault

PLONDKE ERICH JAMES

Methods and systems for allocating interrupts in a multithreaded processor

Partitioned replacement for cache memory

Real time multithreaded scheduler and scheduling method

Configurable translation lookaside buffer

Table call instruction for frequently called functions

Floating point constant generation instruction

CODRESCU LUCIAN

Multithreaded processor with lock indicator

System and method for generating and using predicates within a single instruction packet

System and method to evaluate a data value as an instruction

Selective preclusion of a bus access request

System and method of processing hierarchical very long instruction packets

ZENG MAO

System and method to perform feature detection and to determine a feature score

FIFO load instruction

System and method to determine feature candidate pixels of an image

INGLE AJAY ANANT

System and method to manage a translation lookaside buffer

Systems and methods for cache line replacements

Dual function adder for computing a hardware prefetch address and an arithmetic operation value

KRITHIVASAN SHANKAR

System and method to perform fast rotation operations

Processor and method of determining a normalization count

VENKUMAHANTI SURESH K

Low latency two-level interrupt controller interface to multi-threaded processor

KOOB CHRISTOPHER EDWARD

Computer system with processor local coherency for virtualized input/output

Using the least significant bits of a called function's address to switch processor modes