Multithreaded processor with lock indicator

Abstract

Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.

What is claimed is: 
     
       1. A method comprising:
 receiving a translation lookaside buffer (TLB) miss event associated with a first thread of a multithreaded processor; 
 checking a TLB lock indicator, wherein the TLB lock indicator includes a bit stored at a control register; 
 in response to the TLB lock indicator indicating an unlocked state, allowing access by the first thread to an exception handler associated with a TLB; and 
 in response to the TLB lock indicator indicating a locked state: 
 putting the first thread to sleep, wherein putting the first thread to sleep is performed by a sleep mode circuit in response to receiving a sleep instruction from a control circuit; 
 transitioning the TLB lock indicator from the locked state to the unlocked state; and 
 in response to the TLB lock indicator transitioning from the locked state to the unlocked state, replaying execution of a packet that caused the TLB miss event. 
 
     
     
       2. The method of  claim 1 , further comprising locking setting the TLB lock indicator to the locked state when access is allowed. 
     
     
       3. The method of  claim 1 , wherein checking the TLB lock indicator is performed by the control circuit of the multithreaded processor in response to the TLB miss event. 
     
     
       4. The method of  claim 1 , further comprising, in response to the TLB lock indicator transitioning from the locked state to the unlocked state, waking the first thread and a second thread, wherein an order to wake the first thread and the second thread is determined by a processing order associated with the first thread and the second thread, a thread priority order associated with the first thread and the second thread, or a combination thereof. 
     
     
       5. The method of  claim 1 , further comprising:
 calculating a result related to the TLB miss event; 
 programming the result into the TLB; and 
 setting the TLB lock indicator to the unlocked state. 
 
     
     
       6. The method of  claim 5 , further comprising automatically setting the TLB lock indicator to the unlocked state upon returning from the exception handler. 
     
     
       7. The method of  claim 1 , wherein the exception handler sets the TLB lock indicator to the locked state. 
     
     
       8. A method comprising:
 receiving a translation lookaside buffer (TLB) miss event associated with a thread of a multithreaded processor, the thread having access to a shared translation lookaside buffer (TLB); 
 reading a TLB lock indicator and in response to the TLB lock indicator indicating a locked state, putting the thread to sleep, wherein the TLB lock indicator comprises a bit stored at a control register, and wherein putting the thread to sleep is performed by a sleep mode circuit in response to receiving a sleep instruction from a control circuit; 
 in response to receipt of an instruction, waking the thread; and 
 in response to the TLB lock indicator transitioning from the locked state to an unlocked state, replaying execution of an instruction packet that caused the TLB miss event. 
 
     
     
       9. The method of  claim 8 , wherein the TLB is reserved for a first thread during a first time period, wherein the TLB is reserved for a second thread during a second time period, and wherein a third thread is put to sleep during the first time period and the second time period. 
     
     
       10. The method of  claim 9 , wherein the third thread is awakened during a third time period. 
     
     
       11. The method of  claim 10 , further comprising, after awakening the third thread, replaying execution of an instruction packet that was executed by the third thread prior to the third thread being put to sleep. 
     
     
       12. A method, comprising:
 receiving a translation lookaside buffer (TLB) miss event associated with a first thread of a multithreaded processor; 
 checking a TLB lock indicator, wherein the TLB lock indicator includes a bit stored at a control register, and wherein checking the TLB lock indicator is performed by a control circuit of the multithreaded processor in response to the TLB miss event; 
 if the TLB lock indicator is unlocked, allowing access by the first thread to an exception handler associated with a TLB; 
 if the TLB lock indicator is locked:
 putting the first thread to sleep, wherein putting the first thread to sleep is performed by a sleep mode circuit in response to receiving a sleep instruction from the control circuit; 
 transitioning the TLB lock indicator from a locked state to an unlocked state; and 
 after transitioning the TLB lock indicator from the locked state to the unlocked state, replaying execution of a packet that caused the TLB miss event. 
 
 
     
     
       13. The method of  claim 12 , wherein a value of the bit stored at the control register indicates whether threads of the multithreaded processor are temporarily restricted from modifying all data at the TLB. 
     
     
       14. The method of  claim 12 , wherein replaying execution of the packet that caused the TLB miss event comprises repeating a request to translate a virtual address at the TLB. 
     
     
       15. The method of  claim 12 , wherein the packet is an instruction packet that includes a first instruction and a second instruction. 
     
     
       16. A system comprising:
 a translation lookaside buffer (TLB) shared by multiple processing threads of a multithreaded processor; 
 a TLB lock bit in a register of the multithreaded processor; and 
 a control logic circuit configured to:
 in response to the TLB lock bit having a locked configuration:
 send a sleep instruction to a sleep mode circuit to put a first thread of the multiple processing threads to sleep in response to detecting a first TLB miss event associated with the first thread, 
 transition the TLB lock bit from the locked configuration to an unlocked configuration, and 
 in response to transitioning the TLB lock bit from the locked configuration to the unlocked configuration, replaying an execution packet that caused the first TLB miss event. 
 
 
 
     
     
       17. The system of  claim 16 , wherein the first TLB miss event is associated with the execution packet of the first thread, and wherein the control logic circuit is further configured to store the execution packet and to not increment a program counter associated with the first thread when the first thread is put to sleep. 
     
     
       18. The system of  claim 16 , wherein the first thread is put to sleep without launching an exception handler in response to the first TLB miss event. 
     
     
       19. The system of  claim 16 , wherein the control logic circuit is further configured to set the TLB lock bit to the locked configuration and to concurrently initiate an exception handler associated with the first TLB miss event in response to the TLB lock bit having the unlocked configuration. 
     
     
       20. The system of  claim 19 , wherein the TLB lock bit is configured to be set to the unlocked configuration by an instruction of the exception handler. 
     
     
       21. The system of  claim 19 , wherein the TLB lock bit is configured to be set to the locked configuration by the control logic circuit. 
     
     
       22. The system of  claim 16 , wherein the control logic circuit is configured to store data indicating an order to awaken the first thread when a second thread of the multiple processing threads is also put to sleep in response to a second TLB miss event. 
     
     
       23. The system of  claim 16 , further comprising a first control register that includes:
 a sleep field that indicates whether the first thread is to transition between a sleep state and an active state; 
 an exception field that indicates a type of exception to which the first thread is responsive; and 
 a return address field that indicates an instruction to begin executing after the first thread is awoken. 
 
     
     
       24. A system comprising:
 means for storing a bit indicating a lock status of a shared resource in a multithreaded processor; 
 means for automatically setting the shared resource to a locked state before processing exception handling instructions to handle a processing exception associated with the shared resource; 
 means for saving a state of a thread; 
 means for putting the thread to sleep after the state of the thread has been saved in response to receiving a sleep instruction from a control circuit while the lock status of the shared resource indicates the locked state; 
 means for setting the lock status of the shared resource to the unlocked state; and 
 means for replaying execution of an instruction packet that caused the processing exception associated with the shared resource, in response to the lock status of the shared resource transitioning from the locked state to the unlocked state. 
 
     
     
       25. A computer readable medium having processor executable instructions to cause a processor to:
 handle an exception associated with a resource that is shared by multiple threads of a multithreaded processor; and 
 set a hardware lock associated with the resource to a locked state after the exception has been handled; and 
 in response to the hardware lock indicating the locked state:
 put a first thread of the multiple threads to sleep in response to detecting an exception associated with the resource caused by the first thread, wherein putting the first thread to sleep is performed by a sleep mode circuit in response to receiving a sleep instruction from a control logic circuit; 
 transition the hardware lock from the locked state to an unlocked state, and 
 in response to transitioning the hardware lock from the locked state to the unlocked state, replaying execution of an instruction packet that caused the exception associated with the resource by the first thread. 
 
 
     
     
       26. The computer readable medium of  claim 25 , wherein the hardware lock is configured to be set to the locked state by the control logic circuit of the processor before the exception is handled. 
     
     
       27. The computer readable medium of  claim 25 , wherein the resource that is shared by the multiple threads of the multithreaded processor is a core memory resource of the multithreaded processor. 
     
     
       28. The computer readable medium of  claim 27 , wherein the core memory resource is a translation lookaside buffer (TLB) and wherein the exception is caused by a TLB miss. 
     
     
       29. The computer readable medium of  claim 25 , wherein the hardware lock includes at least one bit of a global register.