Inventor · disambiguated record
Lucian Codrescu
Also filed as: CODRESCU LUCIAN
87 granted patents·24 pending applications·447 citations·filing 2005–2018
99Inventor score
Top patents by PatentIndex Score
111 records- 0194US8639913B2Multi-mode register file for use in branch predictionCODRESCU LUCIAN·Filed 2008·Granted Jan 28, 2014·36 cites·18 claims
- 0292US7676647B2System and method of processing data using scalar/vector instructionsQUALCOMM INC·Filed 2006·Granted Mar 9, 2010·40 cites·32 claims
- 0390US8341353B2System and method to access a portion of a level two memory and a level one memoryVENKUMAHANTI SURESH K·Filed 2010·Granted Dec 25, 2012·15 cites·27 claims
- 0488US8756601B2Memory coherency acceleration via virtual machine migrationPLONDKE ERICH J·Filed 2011·Granted Jun 17, 2014·13 cites·26 claims
- 0588US8397238B2Thread allocation and clock cycle adjustment in an interleaved multi-threaded processorVENKUMAHANTI SURESH K·Filed 2009·Granted Mar 12, 2013·19 cites·39 claims
- 0687US9396012B2Systems and methods of using a hypervisor with guest operating systems and virtual processorsQUALCOMM INC·Filed 2013·Granted Jul 19, 2016·8 cites·43 claims
- 0787US8190854B2System and method of processing data using scalar/vector instructionsCODRESCU LUCIAN·Filed 2010·Granted May 29, 2012·12 cites·32 claims
- 0886US8250332B2Partitioned replacement for cache memoryPLONDKE ERICH JAMES·Filed 2009·Granted Aug 21, 2012·16 cites·27 claims
- 0986US8140823B2Multithreaded processor with lock indicatorCODRESCU LUCIAN·Filed 2007·Granted Mar 20, 2012·16 cites·29 claims
- 1085US8370806B2Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processorQUALCOMM INC·Filed 2006·Granted Feb 5, 2013·17 cites·24 claims
- 1185US7398371B2Shared translation look-aside buffer and methodQUALCOMM INC·Filed 2005·Granted Jul 8, 2008·16 cites·9 claims
- 1284US8341604B2Embedded trace macrocell for enhanced digital signal processor debugging operationsCODRESCU LUCIAN·Filed 2006·Granted Dec 25, 2012·16 cites·37 claims
- 1384US7917907B2Method and system for variable thread allocation and switching in a multithreaded processorQUALCOMM INC·Filed 2005·Granted Mar 29, 2011·14 cites·16 claims
- 1483US8243100B2System and method to perform fast rotation operationsKRITHIVASAN SHANKAR·Filed 2008·Granted Aug 14, 2012·16 cites·26 claims
- 1582US9147123B2System and method to perform feature detection and to determine a feature scoreZENG MAO·Filed 2012·Granted Sep 29, 2015·10 cites·42 claims
- 1682US7657791B2Method and system for a digital signal processor debugging during power transitionsQUALCOMM INC·Filed 2006·Granted Feb 2, 2010·13 cites·32 claims
- 1781US8656145B2Methods and systems for allocating interrupts in a multithreaded processorPLONDKE ERICH JAMES·Filed 2008·Granted Feb 18, 2014·10 cites·22 claims
- 1880US8145874B2System and method of data forwarding within an execution unitVENKUMAHANTI SURESH·Filed 2008·Granted Mar 27, 2012·13 cites·27 claims
- 1979US9626579B2Increasing canny filter implementation speedQUALCOMM INC·Filed 2014·Granted Apr 18, 2017·5 cites·20 claims
- 2078US10133598B2Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systemsQUALCOMM INC·Filed 2016·Granted Nov 20, 2018·2 cites·19 claims
- 2178US8719503B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2012·Granted May 6, 2014·4 cites·20 claims
- 2277US9606818B2Systems and methods of executing multiple hypervisors using multiple sets of processorsQUALCOMM INC·Filed 2013·Granted Mar 28, 2017·4 cites·31 claims
- 2376US9823928B2FIFO load instructionZENG MAO·Filed 2011·Granted Nov 21, 2017·4 cites·23 claims
- 2476US8380966B2Method and system for instruction stuffing operations during non-intrusive digital signal processor debuggingQUALCOMM INC·Filed 2006·Granted Feb 19, 2013·8 cites·35 claims
- 2575US8972642B2Low latency two-level interrupt controller interface to multi-threaded processorVENKUMAHANTI SURESH K·Filed 2011·Granted Mar 3, 2015·4 cites·29 claims
- 2675US7913255B2Background thread processing in a multithread digital signal processorQUALCOMM INC·Filed 2005·Granted Mar 22, 2011·7 cites·24 claims
- 2775US7523295B2Processor and method of grouping and executing dependent instructions in a packetQUALCOMM INC·Filed 2005·Granted Apr 21, 2009·7 cites·22 claims
- 2874US9122486B2Bimodal branch predictor encoded in a branch instructionVENKUMAHANTI SURESH K·Filed 2010·Granted Sep 1, 2015·5 cites·22 claims
- 2974US8266409B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2009·Granted Sep 11, 2012·5 cites·38 claims
- 3073US10114756B2Externally programmable memory management unitQUALCOMM INC·Filed 2013·Granted Oct 30, 2018·3 cites·35 claims
- 3173US8601234B2Configurable translation lookaside bufferPLONDKE ERICH JAMES·Filed 2007·Granted Dec 3, 2013·5 cites·29 claims
- 3273US7590824B2Mixed superscalar and VLIW instruction issuing and processing method and systemQUALCOMM INC·Filed 2005·Granted Sep 15, 2009·6 cites·25 claims
- 3373US7383420B2Processor and method of indirect register read and write operationsQUALCOMM INC·Filed 2005·Granted Jun 3, 2008·6 cites·18 claims
- 3472US9455743B2Dedicated arithmetic encoding instructionQUALCOMM INC·Filed 2014·Granted Sep 27, 2016·2 cites·23 claims
- 3572US9207943B2Real time multithreaded scheduler and scheduling methodPLONDKE ERICH JAMES·Filed 2009·Granted Dec 8, 2015·5 cites·27 claims
- 3671US9235418B2Register files for a digital signal processor operating in an interleaved multi-threaded environmentQUALCOMM INC·Filed 2014·Granted Jan 12, 2016·2 cites·19 claims
- 3771US8417922B2Method and system to combine multiple register units within a microprocessorCODRESCU LUCIAN·Filed 2006·Granted Apr 9, 2013·5 cites·35 claims
- 3868US9367468B2Data cache way predictionQUALCOMM INC·Filed 2013·Granted Jun 14, 2016·2 cites·29 claims
- 3968US8281111B2System and method to execute a linear feedback-shift instructionPLONDKE ERICH·Filed 2008·Granted Oct 2, 2012·6 cites·24 claims
- 4067US9116685B2Table call instruction for frequently called functionsPLONDKE ERICH JAMES·Filed 2011·Granted Aug 25, 2015·2 cites·23 claims
- 4167US8631056B2Processor and method of determining a normalization countKRITHIVASAN SHANKAR·Filed 2008·Granted Jan 14, 2014·4 cites·27 claims
- 4266US8953893B2System and method to determine feature candidate pixels of an imageZENG MAO·Filed 2012·Granted Feb 10, 2015·3 cites·29 claims
- 4366US8656137B2Computer system with processor local coherency for virtualized input/outputKOOB CHRISTOPHER EDWARD·Filed 2011·Granted Feb 18, 2014·2 cites·23 claims
- 4466US7685411B2Multi-mode instruction memory unitQUALCOMM INC·Filed 2005·Granted Mar 23, 2010·3 cites·28 claims
- 4565US8990543B2System and method for generating and using predicates within a single instruction packetCODRESCU LUCIAN·Filed 2008·Granted Mar 24, 2015·3 cites·34 claims
- 4665US8874884B2Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than thresholdVENKUMAHANTI SURESH K·Filed 2011·Granted Oct 28, 2014·2 cites·16 claims
- 4765US7814487B2System and method of executing program threads in a multi-threaded processorQUALCOMM INC·Filed 2005·Granted Oct 12, 2010·3 cites·38 claims
- 4865US7702889B2Shared interrupt control method and system for a digital signal processorQUALCOMM INC·Filed 2005·Granted Apr 20, 2010·3 cites·26 claims
- 4964US9715392B2Multiple clustered very long instruction word processing coreQUALCOMM INC·Filed 2014·Granted Jul 25, 2017·2 cites·24 claims
- 5064US8127117B2Method and system to combine corresponding half word units from multiple register units within a microprocessorZENG MAO·Filed 2006·Granted Feb 28, 2012·3 cites·33 claims
Showing the top 50 of 111 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →