Inventor

CODRESCU LUCIAN

US87 patents

⚠️ This page may combine multiple inventors who share the name “CODRESCU LUCIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CODRESCU LUCIAN

QUALCOMM INC

System and method of processing data using scalar/vector instructions

Systems and methods of using a hypervisor with guest operating systems and virtual processors

Method and system for variable thread allocation and switching in a multithreaded processor

Background thread processing in a multithread digital signal processor

Shared translation look-aside buffer and method

Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging

Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor

Method and system for a digital signal processor debugging during power transitions

Processor and method of grouping and executing dependent instructions in a packet

Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systems

Externally programmable memory management unit

Systems and methods of executing multiple hypervisors using multiple sets of processors

Increasing canny filter implementation speed

Multiple clustered very long instruction word processing core

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Shared interrupt control method and system for a digital signal processor

Multi-mode instruction memory unit

Dedicated arithmetic encoding instruction

Shared interrupt controller for a multi-threaded processor

System and method of selectively accessing a register file

System and method of executing program threads in a multi-threaded processor

Mixed superscalar and VLIW instruction issuing and processing method and system

Method and system for encoding variable length packets with variable instruction sizes

Processor and method of indirect register read and write operations

CODRESCU LUCIAN

Multi-mode register file for use in branch prediction

Multithreaded processor with lock indicator

Embedded trace macrocell for enhanced digital signal processor debugging operations

System and method of processing data using scalar/vector instructions

Method and system to combine multiple register units within a microprocessor

System and method for generating and using predicates within a single instruction packet

ZENG MAO

System and method to perform feature detection and to determine a feature score

FIFO load instruction

System and method to determine feature candidate pixels of an image

Method and system to combine corresponding half word units from multiple register units within a microprocessor

PLONDKE ERICH JAMES

Methods and systems for allocating interrupts in a multithreaded processor

Partitioned replacement for cache memory

Real time multithreaded scheduler and scheduling method

Configurable translation lookaside buffer

VENKUMAHANTI SURESH K

System and method to access a portion of a level two memory and a level one memory

Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor

Low latency two-level interrupt controller interface to multi-threaded processor

Bimodal branch predictor encoded in a branch instruction

KRITHIVASAN SHANKAR

System and method to perform fast rotation operations

Processor and method of determining a normalization count

KOOB CHRISTOPHER EDWARD

Configurable cache and method to configure same

Configurable cache and method to configure same

PLONDKE ERICH J

Memory coherency acceleration via virtual machine migration

VENKUMAHANTI SURESH

System and method of data forwarding within an execution unit

PLONDKE ERICH

System and method to execute a linear feedback-shift instruction

SASSONE PETER G

Hybrid write-through/write-back cache policy managers, and related systems and methods