Inventor

LILAK AARON D

US74 patents

⚠️ This page may combine multiple inventors who share the name “LILAK AARON D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LILAK AARON D

INTEL CORP

Forksheet transistor architectures

Backside contact structures and fabrication for metal on both sides of devices

Backside contacts for semiconductor devices

Semiconductor device with isolated body portion

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors having device strata with different channel widths

Forksheet transistor architectures

Backside contact structures and fabrication for metal on both sides of devices

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Stacked transistors with different gate lengths in different device strata

Structures and methods for memory cells

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

Stacked transistor architecture having diverse fin geometry

Device isolation by fixed charge

Backside contact structures and fabrication for metal on both sides of devices

Backside fin recess control with multi-hsi option

Integrated circuit with stacked transistor devices

Leave-behind protective layer having secondary purpose

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

High concentration indium fluorine retrograde wells

High concentration indium fluorine retrograde wells

Recoiled metal thin film for 3D inductor with tunable core

Structures and methods for memory cells

Backside contact structures and fabrication for metal on both sides of devices

Stacked transistors

Backside contact structures and fabrication for metal on both sides of devices

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

Metallization structures under a semiconductor device layer

Vertical diode in stacked transistor architecture

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor

Stacked transistors

Semiconductor device having stacked transistors and multiple threshold voltage control

Metallization structures under a semiconductor device layer

Systems and methods to reduce FinFET gate capacitance

Methods and apparatus for gettering impurities in semiconductors

Backside fin recess control with multi-HSI option

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

Isolation wall stressor structures to improve channel stress and their methods of fabrication

Leave-behind protective layer having secondary purpose

Metallization structures for stacked device connectivity and their methods of fabrication

Gate-all-around integrated circuit structures having insulator FIN on insulator substrate

Subfin leakage suppression using fixed charge

Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

Vertically stacked memory elements with air gap

Vertically stacked transistors in a fin

Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion