Inventor

MANNEBACH EHREN

US49 patents

⚠️ This page may combine multiple inventors who share the name “MANNEBACH EHREN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANNEBACH EHREN

INTEL CORP

Forksheet transistor architectures

Backside contacts for semiconductor devices

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Stacked forksheet transistors

Stacked nanowire transistor structure with different channel geometries for stress

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors having device strata with different channel widths

Forksheet transistor architectures

Stacked transistors with different gate lengths in different device strata

Stacked transistor structures with asymmetrical terminal interconnects

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Leave-behind protective layer having secondary purpose

Transistors stacked on front-end p-type transistors

Sideways vias in isolation areas to contact interior layers in stacked devices

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Leave-behind protective layer having secondary purpose

Sideways vias in isolation areas to contact interior layers in stacked devices

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process for forming such

Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

Capacitance reduction for semiconductor devices based on wafer bonding

Device including air gapping of gate spacers and other dielectrics and process for providing such

Forming an oxide volume within a fin

Vertically stacked memory elements with air gap

Stacked source-drain-gate connection and process for forming such

Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

Stacked trigate transistors with dielectric isolation between first and second semiconductor fins

Local interconnect with air gap

Stacked transistors with dielectric between channels of different device strata

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Recessed metal interconnects to mitigate EPE-related via shorting

Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact

Contact resistance reduction in transistor devices with metallization on both sides

Backside contacts for semiconductor devices

Self-aligned local interconnects

Pedestal fin structure for stacked transistor integration

Epitaxial layer with substantially parallel sides

Three dimensional integrated circuits with stacked transistors

Stacked transistor architecture including nanowire or nanoribbon thin film transistors

Vertical memory cells

PAINTER PAUL

Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter

Analogue ionic liquids for the separation and recovery of hydrocarbons from particulate matter

PENN STATE RES FOUND

Analogue ionic liquids for the separation and recovery of hydrocarbons from particulate matter

LILAK AARON D

CMOS architecture with thermally stable silicide gate workfunction metal