Inventor
ELLIS JACKSON L
US26 patents
⚠️ This page may combine multiple inventors who share the name “ELLIS JACKSON L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
12 patentsUS6336150B1Jan 1, 2002
Apparatus and method for enhancing data transfer rates using transfer control blocks
LSI LOGIC CORP134 citations98
US5907717AMay 25, 1999
Cross-connected memory system for allocating pool buffers in each frame buffer and providing addresses thereof
LSI LOGIC CORP93 citations98
US6247040B1Jun 12, 2001
Method and structure for automated switching between multiple contexts in a storage subsystem target device
LSI LOGIC CORP103 citations97
US6081849AJun 27, 2000
Method and structure for switching multiple contexts in storage subsystem target device
LSI LOGIC CORP145 citations97
US6029226AFeb 22, 2000
Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command
LSI LOGIC CORP126 citations96
US6449666B2Sep 10, 2002
One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access block
LSI LOGIC CORP66 citations95
US6324594B1Nov 27, 2001
System for transferring data having a generator for generating a plurality of transfer extend entries in response to a plurality of commands received
LSI LOGIC CORP61 citations95
US7181548B2Feb 20, 2007
Command queueing engine
LSI LOGIC CORP23 citations92
US6617893B1Sep 9, 2003
Digital variable clock divider
LSI LOGIC CORP49 citations92
US6148326ANov 14, 2000
Method and structure for independent disk and host transfer in a storage subsystem target device
LSI LOGIC CORP13 citations73
US6112278AAug 29, 2000
Method to store initiator information for SCSI data transfer
LSI LOGIC CORP8 citations72
US5954806ASep 21, 1999
Method to handle SCSI messages as a target
LSI LOGIC CORP8 citations72
NCR CORP
4 patentsUS5420994AMay 30, 1995
Method for reading a multiple byte data element in a memory system with at least one cache and a main memory
NCR CORP21 citations89
US5835945ANov 10, 1998
Memory system with write buffer, prefetch and internal caches
NCR CORP10 citations72
US5953740ASep 14, 1999
Computer memory system having programmable operational characteristics based on characteristics of a central processor
NCR CORP7 citations71
US5434990AJul 18, 1995
Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
NCR CORP11 citations71