Inventor

ROWLANDS JOSEPH B

US57 patents

⚠️ This page may combine multiple inventors who share the name “ROWLANDS JOSEPH B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROWLANDS JOSEPH B

BROADCOM CORP

System on a chip for networking

System on a chip for networking

System on a chip for networking

Source controlled cache allocation

System having interfaces, switch, and memory bridge for CC-NUMA operation

Scalable cache coherent distributed shared memory processing system

Direct access mode for a cache

Coherent shared memory processing system

System having address-based intranode coherency and data-based internode coherency

Programmably disabling one or more cache entries

Cache configured to read evicted cache block responsive to transmitting block&#39;s address on interface

Source controlled cache allocation

Independent reset of arbiters and agents to allow for delayed agent reset

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

Fast arbitration scheme for a bus

Addressing scheme supporting variable local addressing and variable global addressing

Bus precharge during a phase of a clock signal to eliminate idle clock cycle

System having interfaces and switch that separates coherent and packet traffic

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

Direct access mode for a cache

Deterministic setting of replacement policy in a cache

Deterministic setting of replacement policy in a cache through way selection

Read exclusive for fast, simple invalidate

System on a chip for networking

Load-linked/store conditional mechanism in a CC-NUMA system

Programmably disabling one or more cache entries

Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

Distributed copies of configuration information using token ring

Ambiguous virtual channels

L2 cache maintaining local ownership of remote coherency blocks

System having interfaces, switch, and memory bridge for CC-NUMA operation

Addressing scheme supporting fixed local addressing and variable global addressing

Bus sampling on one edge of a clock signal and driving on another edge

Source triggered transaction blocking

Bus sampling on one edge of a clock signal and driving on another edge

Default bus grant to a bus agent

Data pend mechanism

System having interfaces and switch that separates coherent and packet traffic

Random generator

Read exclusive for fast, simple invalidate

Cache programmable to partition ways to agents and/or local/remote blocks

Bridges performing remote reads and writes as uncacheable coherent operations

Transparent data format within host device supporting differing transaction types

Ambiguous virtual channels

Remote line directory which covers subset of shareable CC-NUMA memory space

SUN MICROSYSTEMS INC

Re-fetching cache memory enabling low-power modes

Reduced-power memory with per-sector ground control

Reduced-power memory with per-sector power/ground control and early address

ORACLE AMERICA INC

Re-fetching cache memory enabling alternative operational modes

Re-fetching cache memory having coherent re-fetching

Cache configured to read evicted cache block responsive to transmitting block's address on interface