Inventor

CHAWLA NITIN

IN37 patents

⚠️ This page may combine multiple inventors who share the name “CHAWLA NITIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAWLA NITIN

ST MICROELECTRONICS INT NV

In-memory compute array with integrated bias elements

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

In-memory computation circuit using static random access memory (SRAM) array segmentation

In-memory compute array with integrated bias elements

Bit-cell architecture based in-memory compute

Memory management device, system and method

In-memory compute array with integrated bias elements

Memory management device, system and method

Streaming access memory device, system and method

Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive multi-stage slack borrowing for high performance error resilient computing

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

At-speed transition fault testing for a multi-port and multi-clock memory

Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

ST MICROELECTRONICS SRL

Elements for in-memory compute

Tagged memory operated at lower VMIN in error tolerant system

Computing system power management device, system and method

Variable clock adaptation in neural network processors

Tagged memory operated at lower vmin in error tolerant system

Elements for in-memory compute

Computing system power management device, system and method

Tagged memory operated at lower vmin in error tolerant system

Deep convolutional network heterogeneous architecture

ST MICROELECTRONICS PVT LTD

Spread spectrum clock generation

Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry

Device for implementing a sum of products expression

CHAWLA NITIN

Fail safe adaptive voltage/frequency system

Calibration arrangement

Fail safe adaptive voltage/frequency system

PARTHASARATHY CHITTOOR

Adaptive multi-stage slack borrowing for high performance error resilient computing