Memory management device, system and method

Abstract

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

The invention claimed is: 
     
       1. A device, comprising:
 a memory having a memory array organized as a plurality of rows intersecting a plurality of columns, wherein, in operation, memory cells of a cut of the memory array store information indicative of reliability types of regions of the memory, including information indicative of reliability types of regions of the memory array; and 
 control circuitry coupled to the memory, wherein the control circuitry, in operation, responds to a request to allocate memory to a process sharing the memory by:
 determining a request type associated with the request to allocate memory; and 
 allocating memory to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types stored in the cut of the memory array. 
 
 
     
     
       2. The device of  claim 1 , wherein the memory comprises a second memory array and, in operation, the cut of the memory array stores information indicative of reliability types of regions of the second memory array. 
     
     
       3. The device of  claim 1 , wherein, in operation, the cut of the memory array stores information indicative of a reliability type of a region of the memory array spanning a subset of the rows of the memory array and a subset of the columns of the memory array. 
     
     
       4. The device of  claim 3 , wherein the subset of the rows of the memory array is discontinuous. 
     
     
       5. The device of  claim 4 , wherein the subset of the columns of the memory array is discontinuous. 
     
     
       6. The device of  claim 3 , wherein the subset of the columns of the memory array is discontinuous. 
     
     
       7. The device of  claim 1 , wherein the cut of the memory array, in operation, stores the information indicative of reliability-types of regions of the memory array as one or more memory maps. 
     
     
       8. The device of  claim 1 , wherein the determining a request type comprises determining a type of process associated with the request. 
     
     
       9. The device of  claim 8 , wherein the control circuitry, in operation:
 responds to a request received from a host system process by allocating from one or more regions of the memory which the stored reliability information indicates has a first reliability-type. 
 
     
     
       10. The device of  claim 9 , wherein the control circuitry, in operation:
 responds to a request received from an application process by allocating from one or more regions of the memory which the stored reliability information indicates has the first reliability-type or a second reliability type, the second reliability type indicating the region is less-reliable than a region having the first reliability-type. 
 
     
     
       11. The device of  claim 9 , wherein the control circuitry, in operation:
 responds to a request received from an artificial neural network (ANN) control process by allocating from one or more regions of the memory which the stored reliability information indicates has the first reliability-type; and 
 responds to a request from an ANN process to allocate memory to a memory buffer to store kernel data, intermediate partial sums, or feature data by allocating from one or more regions of the memory which the stored reliability information indicates has the first reliability-type or a second reliability type, the second reliability type indicating the region is less-reliable than a region having the first reliability-type. 
 
     
     
       12. The device of  claim 1 , wherein the stored information indicative of reliability-types of regions of the memory indicates one of a plurality of reliability levels associated with regions of the memory. 
     
     
       13. The device of  claim 1 , comprising built-in-self-test circuitry, which, in operation, periodically:
 tests the memory; and 
 updates the stored information indicative of the reliability of regions of the memory based on results of the testing. 
 
     
     
       14. The device of  claim 1 , wherein the memory array is a non-volatile memory array. 
     
     
       15. A system, comprising:
 one or more processing cores; 
 a memory, coupled to the one or more processing cores and including a memory array organized as an array of a plurality of rows of memory cells intersecting a plurality of columns of memory cells, wherein, in operation, memory cells of a cut of the memory array store information indicative of reliability types of regions of the memory, including information indicative of reliability types of regions of the memory array; and 
 control circuitry coupled to the memory and to the one or more processing cores, wherein the control circuitry, in operation, responds to a request to allocate memory to a process sharing the memory by:
 determining a request type associated with the request to allocate memory; and 
 allocating memory to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory stored in the cut of the memory array. 
 
 
     
     
       16. The system of  claim 15  wherein the determining a request type comprises determining a type of process associated with the request. 
     
     
       17. The system of  claim 15 , wherein the memory comprises a second memory array and, in operation, the cut of the memory array stores information indicative of reliability types of regions of the second memory array. 
     
     
       18. A method, comprising:
 storing information indicative of reliability types of regions of a memory in a cut of a memory array of the memory, the memory array being organized as a plurality of rows of memory cells intersecting a plurality of columns of memory cells and the information indicative of reliability types of regions of the memory including information indicative of reliability types of regions of the memory array; and 
 responding to a request to allocate memory to a process of a plurality of processes sharing the memory by:
 determining a request type associated with the request to allocate memory; and 
 allocating memory to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory stored in the cut of the memory array. 
 
 
     
     
       19. The method of  claim 18 , wherein the determining a request type comprises determining a type of process associated with the request. 
     
     
       20. The method of  claim 18 , wherein the memory comprises a second memory array and the information indicative of reliability types of regions of the memory includes information indicative of reliability types of regions of the second memory array. 
     
     
       21. A non-transitory computer-readable medium having contents which cause memory management circuitry to perform a method, the method comprising:
 storing information indicative of reliability types of regions of a memory in a cut of a memory array of the memory, the memory array being organized as a plurality of rows of memory cells intersecting a plurality of columns of memory cells and the information indicative of reliability types of regions of the memory including information indicative of reliability types of regions of the memory array; and 
 responding to a request to allocate memory to a process of a plurality of processes sharing the memory by:
 determining a request type associated with the request to allocate memory; and 
 allocating memory to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory stored in the cut of the memory array. 
 
 
     
     
       22. The non-transitory computer-readable medium of  claim 21 , wherein the contents comprise instructions executed by the memory management circuitry. 
     
     
       23. The non-transitory computer-readable medium of  claim 21 , wherein the plurality of processes include host system processes and artificial neural network processes. 
     
     
       24. The non-transitory computer-readable medium of  claim 21 , wherein the storing information indicative of reliability types of regions of a memory comprises storing the information indicative of reliability-types of regions of the memory array as one or more memory maps. 
     
     
       25. The non-transitory computer-readable medium of  claim 21 , wherein the memory comprises a second memory array and the information indicative of reliability types of regions of the memory includes information indicative of reliability types of regions of the second memory array. 
     
     
       26. The method of  claim 18 , wherein the storing information indicative of reliability types of regions of a memory comprises storing the information indicative of reliability-types of regions of the memory array as one or more memory maps. 
     
     
       27. The system of  claim 15 , wherein the cut of the memory array, in operation, stores the information indicative of reliability-types of regions of the memory array as one or more memory maps.