Inventor · disambiguated record
Nitin Chawla
Also filed as: CHAWLA NITIN
36 granted patents·12 pending applications·59 citations·filing 2005–2025
95Inventor score
Files withST MICROELECTRONICS INT NV32ST MICROELECTRONICS SRL9CHAWLA NITIN3ST MICROELECTRONICS PVT LTD3PARTHASARATHY CHITTOOR1
Top patents by PatentIndex Score
48 records- 0195US11094376B2In-memory compute array with integrated bias elementsST MICROELECTRONICS INT NV·Filed 2020·Granted Aug 17, 2021·6 cites·21 claims
- 0289US11984151B2Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·3 cites·32 claims
- 0388US12087356B2Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Sep 10, 2024·2 cites·33 claims
- 0486US11474788B2Elements for in-memory computeST MICROELECTRONICS SRL·Filed 2020·Granted Oct 18, 2022·2 cites·17 claims
- 0583US8154335B2Fail safe adaptive voltage/frequency systemCHAWLA NITIN·Filed 2009·Granted Apr 10, 2012·13 cites·22 claims
- 0681US11605424B2In-memory compute array with integrated bias elementsST MICROELECTRONICS INT NV·Filed 2021·Granted Mar 14, 2023·1 cites·20 claims
- 0778US12386506B2Tagged memory operated at lower VMIN in error tolerant systemST MICROELECTRONICS SRL·Filed 2023·Granted Aug 12, 2025·0 cites·22 claims
- 0878US11900240B2Variable clock adaptation in neural network processorsST MICROELECTRONICS SRL·Filed 2020·Granted Feb 13, 2024·1 cites·23 claims
- 0978US8269545B2Fail safe adaptive voltage/frequency systemCHAWLA NITIN·Filed 2011·Granted Sep 18, 2012·5 cites·20 claims
- 1076US2025308574A1Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1174US7698355B2Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetryST MICROELECTRONICS PVT LTD·Filed 2005·Granted Apr 13, 2010·9 cites·11 claims
- 1273US11836346B2Tagged memory operated at lower vmin in error tolerant systemST MICROELECTRONICS SRL·Filed 2022·Granted Dec 5, 2023·0 cites·13 claims
- 1373US11829730B2Elements for in-memory computeST MICROELECTRONICS SRL·Filed 2022·Granted Nov 28, 2023·0 cites·28 claims
- 1473US9021324B2Calibration arrangementCHAWLA NITIN·Filed 2010·Granted Apr 28, 2015·4 cites·24 claims
- 1570US8037336B2Spread spectrum clock generationST MICROELECTRONICS PVT LTD·Filed 2007·Granted Oct 11, 2011·8 cites·20 claims
- 1668US2025078883A1Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1767US11360667B2Tagged memory operated at lower vmin in error tolerant systemST MICROELECTRONICS SRL·Filed 2020·Granted Jun 14, 2022·0 cites·26 claims
- 1867US2025174269A1Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1966US2024395319A1Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 2066US2025069678A1Built-in self test circuit for segmented static random access memory (sram) array input/outputST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 2165US12243584B2In-memory compute array with integrated bias elementsST MICROELECTRONICS INT NV·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 2265US12183424B2Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 31, 2024·0 cites·33 claims
- 2365US11726543B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2020·Granted Aug 15, 2023·0 cites·19 claims
- 2464US12292780B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2023·Granted May 6, 2025·0 cites·14 claims
- 2564US11749343B2Memory management device, system and methodST MICROELECTRONICS INT NV·Filed 2022·Granted Sep 5, 2023·0 cites·27 claims
- 2663US12437825B2At-speed transition fault testing for a multi-port and multi-clock memoryST MICROELECTRONICS INT NV·Filed 2023·Granted Oct 7, 2025·0 cites·40 claims
- 2762US12482518B2Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read currentST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 25, 2025·0 cites·12 claims
- 2862US12469545B2Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 11, 2025·0 cites·42 claims
- 2962US12170120B2Built-in self test circuit for segmented static random access memory (SRAM) array input/outputST MICROELECTRONICS INT NV·Filed 2023·Granted Dec 17, 2024·0 cites·38 claims
- 3062US11257543B2Memory management device, system and methodST MICROELECTRONICS INT NV·Filed 2020·Granted Feb 22, 2022·0 cites·33 claims
- 3162US7917569B2Device for implementing a sum of products expressionST MICROELECTRONICS PVT LTD·Filed 2005·Granted Mar 29, 2011·3 cites·26 claims
- 3260US12237007B2Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Feb 25, 2025·0 cites·39 claims
- 3359US12354644B2Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 8, 2025·0 cites·30 claims
- 3459US8552765B2Adaptive multi-stage slack borrowing for high performance error resilient computingPARTHASARATHY CHITTOOR·Filed 2011·Granted Oct 8, 2013·2 cites·15 claims
- 3559US2025364068A1Randomized data polarity inversion of computational weight data in a digital in-memory computation processing systemST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 3659US2025372158A1Scrambled dummy column memory architecture for an in-memory computation processing systemST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 3758US11823771B2Streaming access memory device, system and methodST MICROELECTRONICS INT NV·Filed 2021·Granted Nov 21, 2023·0 cites·33 claims
- 3858US2025362707A1Tiled in-memory computation processing system with randomized clock staggering and output bindingST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 3956US12353341B2Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selectionST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 4054US12406705B2In-memory computation circuit using static random access memory (SRAM) array segmentationST MICROELECTRONICS INT NV·Filed 2023·Granted Sep 2, 2025·0 cites·24 claims
- 4154US12118451B2Deep convolutional network heterogeneous architectureST MICROELECTRONICS SRL·Filed 2017·Granted Oct 15, 2024·0 cites·24 claims
- 4248US12361982B2Memory architecture supporting both conventional memory access mode and digital in-memory computation processing modeST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 4348US8994416B2Adaptive multi-stage slack borrowing for high performance error resilient computingST MICROELECTRONICS INT NV·Filed 2013·Granted Mar 31, 2015·0 cites·5 claims
- 4446US2024177769A1Bit line accumulation readout scheme for an analog in-memory computation processing circuitST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4544US2023386565A1In-memory computation circuit using static random access memory (sram) array segmentation and local compute tile read based on weighted currentST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4644US2024112728A1Analog in-memory computation processing circuit using segmented memory architectureST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4744US2023386566A1Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4842US12176025B2Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 24, 2024·0 cites·51 claims
Join the waitlist — get patent alerts
Get an alert when Nitin Chawla files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →