Inventor

BIRRITTELLA MARK S

US37 patents

⚠️ This page may combine multiple inventors who share the name “BIRRITTELLA MARK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BIRRITTELLA MARK S

MOTOROLA INC

Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers

ECL to TTL voltage level translator

Fabricating a semiconductor device with buried oxide

Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact

NPN bandgap voltage generator

Gallium arsenide bipolar ECL circuit structure

Monolithic bipolar SCR memory cell

Bipolar memory cell

Selectable write current source for bipolar rams

Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection

Bipolar ram cell and process

Bipolar transient driver

Bipolar RAM cell

Bipolar RAM cell

Complex direct coupled transistor logic

INTEL CORP

Exascale fabric time synchronization

Lane error detection and lane removal mechanism to reduce the probability of data corruption

Reliable transport of ethernet packet data with wire-speed and packet data rate match

Lane error detection and lane removal mechanism to reduce the probability of data corruption

Link transfer, bit error detection and link retry using flit bundles asynchronous to link fabric packets

Multichip package link

Reliable transport of ethernet packet data with wire-speed and packet data rate match

Efficient link layer retry protocol utilizing implicit acknowledgements

Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks

Efficient link layer retry protocol utilizing implicit acknowledgements

Coordinating width changes for an active network link

CRAY RESEARCH INC

System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel

Networked multiprocessor system with global distributed memory and block transfer engine

Multiprocessor computer system with interleaved processing element nodes

ECL latch with single-ended and differential inputs

Read-while-write ram cell

Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families

CRAY INC

Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor

Clock signal duty cycle adjust circuit

Systems and methods for phase detector circuit with reduced offset

Transistor level verilog

SILICON GRAPHICS INC

Circuit design for high-speed digital communication