ECL latch with single-ended and differential inputs

Abstract

An ECL circuit is capable of simultaneously responding to single-ended and differential inputs. The ECL circuit comprises a single-ended input, a differential input, logic responsive to the single-ended and differential inputs for determining a digital output state, and an output for communicating the output state to external devices. Each input, i.e., the single-ended input and the two complementary portions of the differential input, provide a base voltage for a control transistor. In order to allow the single-ended input to override the differential input, the differential input has half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input. In this way, an active single-ended input will exert more control over the current paths than the differential input. When the single-ended input is inactive, the differential input will exert control over the current paths.

What is claimed is: 
     
       1. An ECL latch, comprising: (a) data input means for receiving a data signal;   (b) single-ended input means for receiving a single-ended signal;   (c) differential input means for receiving a differential signal;   (d) data storage means connected to said data input means, differential input means, and single-ended input means for storing a logic state of said data signal in response to said single-ended signal so that an active said single-ended signal overrides said differential signal and determines said logic state according to said data input signal, and wherein said differential signal determines said logic state according to said data input state when said single-ended signal is inactive; and   (e) output means connected to said data storage means for communicating said stored logic level to external devices.   
     
     
       2. An ECL device, comprising: a first transistor and a second transistor connected as a differential pair;   differential input means including a third transistor and a fourth transistor for receiving a differential signal having a high and low level and for driving said first transistor and secondary transistor; and   single ended input means including a fifth transistor connected in parallel to said third transistor for receiving a single-ended signal having a high level that is higher than said high level of said differential signal and a low level that is lower than said high level of said differential signal and for driving said first transistor.   
     
     
       3. An ECL device, comprising: a first transistor and a second transistor connected as a differential pair;   first input means for receiving a differential signal, said first input means including a third transistor and a fourth transistor, said fourth transistor for driving said second transistor of said differential pair;   second input means including a fifth transistor for receiving a single-ended signal, said fifth transistor connected in parallel with said third transistor to drive said first transistor of said differential pair, wherein said single-ended signal has twice the voltage swing of said differential signal,   said differential pair being responsive to said first and second input means for determining a digital output state, wherein an active said single-ended signal overrides said differential signal and determines said digital output state, and wherein said differential signal determines said digital output state when said single-ended signal is inactive; and   output means connected to said differential pair for communicating the digital output state to external devices.   
     
     
       4. An ECL logic gate constructed of transistors, each transistor having an emitter, collector and base, comprising: a first transistor and a second transistor connected as a differential transistor pair with the emitter of the first transistor connected to the emitter of the second transistor, and with the collector of the first transistor and the collector of the second transistor connected for receiving current from a voltage source;   a third transistor having its emitter connected to the base of the first transistor and having its collector connected for receiving current from the voltage source;   a fourth transistor having its emitter connected to the base of the second transistor and having its collector connected for receiving current from the voltage source;   differential input means connected to the base of the third transistor and the base of the fourth transistor for receiving a differential input signal;   a fifth transistor also having its emitter connected to the base of the first transistor and having its collector connected for receiving current from the voltage source; and   single-ended input means connected to the base of the fifth transistor for receiving a single-ended input signal.