Inventor · disambiguated record
Mark S. Birrittella
Also filed as: BIRRITTELLA MARK S
37 granted patents·1 pending application·820 citations·filing 1984–2016
98Inventor score
Top patents by PatentIndex Score
38 records- 0197US4663831AMethod of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layersMOTOROLA INC·Filed 1985·Granted May 12, 1987·154 cites·9 claims
- 0295US10372647B2Exascale fabric time synchronizationINTEL CORP·Filed 2015·Granted Aug 6, 2019·17 cites·25 claims
- 0390US5583990ASystem for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channelCRAY RESEARCH INC·Filed 1993·Granted Dec 10, 1996·150 cites·9 claims
- 0489US9946676B2Multichip package linkINTEL CORP·Filed 2015·Granted Apr 17, 2018·8 cites·25 claims
- 0589US9887804B2Lane error detection and lane removal mechanism to reduce the probability of data corruptionINTEL CORP·Filed 2016·Granted Feb 6, 2018·6 cites·58 claims
- 0686US9628382B2Reliable transport of ethernet packet data with wire-speed and packet data rate matchINTEL CORP·Filed 2014·Granted Apr 18, 2017·7 cites·30 claims
- 0785US10305802B2Reliable transport of ethernet packet data with wire-speed and packet data rate matchINTEL CORP·Filed 2016·Granted May 28, 2019·4 cites·52 claims
- 0884US9819452B2Efficient link layer retry protocol utilizing implicit acknowledgementsINTEL CORP·Filed 2016·Granted Nov 14, 2017·4 cites·42 claims
- 0984US9306863B2Link transfer, bit error detection and link retry using flit bundles asynchronous to link fabric packetsINTEL CORP·Filed 2013·Granted Apr 5, 2016·7 cites·50 claims
- 1084US5797035ANetworked multiprocessor system with global distributed memory and block transfer engineCRAY RESEARCH INC·Filed 1996·Granted Aug 18, 1998·91 cites·18 claims
- 1183US4644194AECL to TTL voltage level translatorMOTOROLA INC·Filed 1985·Granted Feb 17, 1987·33 cites·2 claims
- 1279US9325449B2Lane error detection and lane removal mechanism to reduce the probability of data corruptionINTEL CORP·Filed 2013·Granted Apr 26, 2016·5 cites·30 claims
- 1379US5737628AMultiprocessor computer system with interleaved processing element nodesCRAY RESEARCH INC·Filed 1996·Granted Apr 7, 1998·91 cites·1 claims
- 1471US9397792B2Efficient link layer retry protocol utilizing implicit acknowledgementsINTEL CORP·Filed 2013·Granted Jul 19, 2016·2 cites·35 claims
- 1571US4628248ANPN bandgap voltage generatorMOTOROLA INC·Filed 1985·Granted Dec 9, 1986·25 cites·15 claims
- 1669US6266759B1Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processorCRAY INC·Filed 1998·Granted Jul 24, 2001·55 cites·30 claims
- 1767US10230665B2Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networksINTEL CORP·Filed 2013·Granted Mar 12, 2019·2 cites·29 claims
- 1864US4593457AMethod for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contactMOTOROLA INC·Filed 1984·Granted Jun 10, 1986·24 cites·9 claims
- 1962US4635087AMonolithic bipolar SCR memory cellMOTOROLA INC·Filed 1984·Granted Jan 6, 1987·15 cites·9 claims
- 2059US4717677AFabricating a semiconductor device with buried oxideMOTOROLA INC·Filed 1985·Granted Jan 5, 1988·24 cites·3 claims
- 2157US4649411AGallium arsenide bipolar ECL circuit structureMOTOROLA INC·Filed 1984·Granted Mar 10, 1987·13 cites·7 claims
- 2256US6992515B1Clock signal duty cycle adjust circuitCRAY INC·Filed 2003·Granted Jan 31, 2006·7 cites·38 claims
- 2353US7587305B2Transistor level verilogCRAY INC·Filed 2002·Granted Sep 8, 2009·5 cites·21 claims
- 2452US4580244ABipolar memory cellMOTOROLA INC·Filed 1984·Granted Apr 1, 1986·8 cites·14 claims
- 2548US6836153B2Systems and methods for phase detector circuit with reduced offsetCRAY INC·Filed 2003·Granted Dec 28, 2004·5 cites·49 claims
- 2645US4631570AIntegrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnectionMOTOROLA INC·Filed 1984·Granted Dec 23, 1986·11 cites·1 claims
- 2745US2016132072A1Link layer signal synchronizationINTEL CORP·Filed 2014·Application pending·0 cites
- 2843US10491472B2Coordinating width changes for an active network linkINTEL CORP·Filed 2015·Granted Nov 26, 2019·0 cites·19 claims
- 2942US4598213ABipolar transient driverMOTOROLA INC·Filed 1984·Granted Jul 1, 1986·5 cites·5 claims
- 3042US4570238ASelectable write current source for bipolar ramsMOTOROLA INC·Filed 1985·Granted Feb 11, 1986·7 cites·20 claims
- 3141US6775339B1Circuit design for high-speed digital communicationSILICON GRAPHICS INC·Filed 1999·Granted Aug 10, 2004·14 cites·19 claims
- 3238US4656495ABipolar ram cell and processMOTOROLA INC·Filed 1985·Granted Apr 7, 1987·5 cites·3 claims
- 3335US4697251ABipolar RAM cellMOTOROLA INC·Filed 1985·Granted Sep 29, 1987·5 cites·4 claims
- 3434US4964081ARead-while-write ram cellCRAY RESEARCH INC·Filed 1989·Granted Oct 16, 1990·4 cites·16 claims
- 3533US5177380AECL latch with single-ended and differential inputsCRAY RESEARCH INC·Filed 1992·Granted Jan 5, 1993·2 cites·4 claims
- 3632US4641047AComplex direct coupled transistor logicMOTOROLA INC·Filed 1984·Granted Feb 3, 1987·1 cites·1 claims
- 3730US4701882ABipolar RAM cellMOTOROLA INC·Filed 1985·Granted Oct 20, 1987·2 cites·6 claims
- 3828US5182473AEmitter emitter logic (EEL) and emitter collector dotted logic (ECDL) familiesCRAY RESEARCH INC·Filed 1992·Granted Jan 26, 1993·2 cites·36 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →