Inventor

HUANG CHIEN-CHAO

TW61 patents

⚠️ This page may combine multiple inventors who share the name “HUANG CHIEN-CHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG CHIEN-CHAO

TAIWAN SEMICONDUCTOR MFG

Method of forming a shallow trench isolation structure

Transistor mobility improvement by adjusting stress in shallow trench isolation

Method for dicing semiconductor wafers

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Strained channel on insulator device

CMOS device

Phase change random access memory

Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Strained silicon device manufacturing method

Substrate contact and method of forming the same

Strained silicon layer semiconductor product employing strained insulator layer

Relaxed silicon germanium substrate with low defect density

Slim spacer device and manufacturing method

CMOS device with raised source and drain regions

CMOS devices with graded silicide regions

Transistor mobility improvement by adjusting stress in shallow trench isolation

Relaxed silicon germanium substrate with low defect density

Strained silicon MOS devices

Back end IC wiring with improved electro-migration resistance

Strained channel on insulator device

Semiconductor device employing an extension spacer and a method of forming the same

Semiconductor device with modified channel compressive stress

Shallow trench isolation structure for semiconductor device

Microelectronic device and a method for its manufacture

Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Cobalt silicidation process for substrates with a silicon—germanium layer

Method for forming SOI device

Semiconductor flash device

Method for forming semiconductor device with modified channel compressive stress

Method for controlling phase angle of a mask by post-treatment

Aluminum based conductor for via fill and interconnect

Method for preparing mask and wafer data files

UNITED MICROELECTRONICS CORP

Alignment mark design

Method of producing phase shifting mask

Alternating phase-shifting mask

Method for manufacturing metal oxide semiconductor transistor having raised source/drain

Method of fabricating a MOS transistor having SEG silicon

Method of fabricating a phase shift mask utilizing a defect repair machine

Method for manufacturing phase-shifting mask

Method of aligning a mask in photolithographic process

Method of manufacturing binary phase shift mask

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device having semiconductor alloy layer adjacent a gate structure

Semiconductor device with silicided source/drain region

Cobalt silicidation process for substrates comprised with a silicon-germanium layer

HUANG CHIEN-CHAO

Strained gate electrodes in semiconductor devices

Strained silicon device

TU CHIH-CHIANG

Mask making decision for manufacturing (DFM) on mask quality control

Mask making decision for manufacturing (DFM) on mask quality control

LIANG CHUN SHENG

CMOS device with raised source and drain regions