Inventor

BARRICK BRIAN D

US74 patents

⚠️ This page may combine multiple inventors who share the name “BARRICK BRIAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARRICK BRIAN D

IBM

Managing a free list of resources to decrease control complexity and reduce power consumption

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

Dual-issuance of microprocessor instructions using dual dependency matrices

Handling and fusing load instructions in a processor

Check pointing of accumulator register results in a microprocessor

Freelist based global completion table having both thread-specific and global completion table identifiers

Program counter (PC)-relative load and store addressing for fused instructions

Fusion to enhance early address generation of load instructions in a microprocessor

Logical register recovery within a processor

Cache miss thread balancing

In-pipe error scrubbing within a processor core

Direct register restore mechanism for distributed history buffers

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Assignment of microprocessor register tags at issue time

Fast mapper restore for flush in processor

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

Inferring future value for speculative branch resolution in a microprocessor

Fast perfect issue of dependent instructions in a distributed issue queue system

Assignment of microprocessor register tags at issue time

Slice-based allocation history buffer

Pairing issue queues for complex instructions and instruction fusion

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Register file write using pointers

Slice-based allocation history buffer

Merging status and control data in a reservation station

Data-less history buffer with banked restore ports in a register mapper

Multi-level history buffer for transaction memory in a microprocessor

Asynchronous flush and restore of distributed history buffer

Execution elision of intermediate instruction by processor

Logical register recovery within a processor

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Cache miss thread balancing

Supporting speculative microprocessor instruction execution

System and handling of register data in processors

On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Operation of a multi-slice processor with reduced flush and restore latency

Operation of a multi-slice processor with reduced flush and restore latency

Freelist based global completion table having both thread-specific and global completion table identifiers

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Store data forwarding with no memory model restrictions

Inferring future value for speculative branch resolution

Dependency skipping execution

ALEXANDER GREGORY W

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

TSAI AARON

Store data forwarding with no memory model restrictions

BARRICK BRIAN D

Intermediate register mapper