Inventor

FASTOW RICHARD

US61 patents

⚠️ This page may combine multiple inventors who share the name “FASTOW RICHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FASTOW RICHARD

ADVANCED MICRO DEVICES INC

Low column leakage nor flash array-double cell implementation

Automatic program disturb with intelligent soft programming for flash cells

Minimization of FG-FG coupling in flash memory

Threshold voltage compacting for non-volatile semiconductor memory designs

Memory device with an alternating Vss interconnection

Flash memory array architecture having staggered metal lines

2Bit/cell architecture for floating gate flash memory product and associated method

Low column leakage NOR flash array-single cell implementation

Nitridization of the pre-ddi screen oxide

Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells

Flash memory cells having a modulation doped heterojunction structure

Method of channel hot electron programming for short channel NOR flash arrays

Feedback method to optimize electric field during channel erase of flash memory devices

Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process

Low column leakage flash memory array

Method of programming memory cells

Virtual ground silicide bit line process for floating gate flash memory

Accurate verify apparatus and method for NOR flash memory cells in the presence of high column leakage

Method for reducing short channel effects in memory cells and related structure

Memory array with buried bit lines

Method of matching core cell and reference cell source resistances

High density flash EEPROM array with source side injection

NOR array with buried trench source line

APDE scheme for flash memory application

Method and system for applying testing voltage signal

Method of programming a memory cell

SPANSION LLC

Method, system, and circuit for performing a memory related operation

Method for minimizing false detection of states in flash memory devices

Recognition of speech with different accents

Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell

Parallel bitline nonvolatile memory employing channel-based processing technology

CT-NOR differential bitline sensing architecture

Data pattern analysis

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

FASTOW RICHARD

Real-time data pattern analysis system and method of operation thereof

High read speed electronic memory with serial array transistors

Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

Arithmetic logic unit architecture

High read speed memory with gate isolation

High density NOR flash array architecture

High density NOR flash array architecture

INTEL CORP

Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding

Memory arrays with bonded and shared logic circuitry

Block by deck operations for NAND memory

Flash memory components and methods

Memory device and method for erasing memory

Reducing power consumption in nonvolatile memory due to standby leakage current

Intel NDTM US LLC

Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device

Weak erase pulse

NAZARIAN HAGOP

Parallel bitline nonvolatile memory employing channel-based processing technology