Reducing power consumption in nonvolatile memory due to standby leakage current

Abstract

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

What is claimed is: 
     
       1. A nonvolatile memory device comprising:
 a memory die having nonvolatile memory cells, the memory die including circuitry having current leakage when the memory die is in a standby state where the memory die is ready to receive an access command to execute; and 
 power gating circuitry to selectively transition the memory die from the standby state to a deep power down state, where the memory die is to ignore all access commands, in response to a trigger from a timer, the timer to track a standby time in response to entry of the memory die into the standby state, the timer to trigger the transition to the deep power down state based on an amount of time in the standby state, the amount of time based on command type. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , wherein the circuitry having current leaking comprises CMOS (complementary metal oxide semiconductor) control circuitry on the memory die. 
     
     
       3. The nonvolatile memory device of  claim 1 , wherein the amount of time is dynamically programmable. 
     
     
       4. The nonvolatile memory device of  claim 1 , wherein the nonvolatile memory cells include NAND (not AND) memory cells. 
     
     
       5. The nonvolatile memory device of  claim 1 , wherein the timer is part of the memory die. 
     
     
       6. The nonvolatile memory device of  claim 1 , wherein a storage controller to control multiple memory dies controls selective transition by the power gating circuitry. 
     
     
       7. The nonvolatile memory device of  claim 1 , wherein for standby after a program command, the timer is to track the standby time only if a program operation is verified for the program command. 
     
     
       8. The nonvolatile memory device of  claim 1 , wherein the amount of time comprises at least five times a read time for the memory die. 
     
     
       9. A system, comprising:
 multiple memory dies having nonvolatile memory cells, the memory dies including circuitry having current leakage when the memory die is in a standby state where the memory die is ready to receive an access command to execute; and 
 a timer to track a standby time in response to entry of one of the multiple dies into the standby state, the timer to trigger a transition of the one of the multiple memory dies to a deep power down state after a amount of time in the standby state, wherein the memory die is to ignore all access commands in the deep power down state and the amount of time is based on command type. 
 
     
     
       10. The system of  claim 9 , wherein the circuitry having current leaking comprises CMOS (complementary metal oxide semiconductor) control circuitry on the memory die. 
     
     
       11. The system of  claim 9 , wherein the amount of time is dynamically programmable. 
     
     
       12. The system of  claim 9 , wherein the amount of time is different for a standby state after an array command than for a standby after an I/O (input/output) command. 
     
     
       13. The system of  claim 12 , wherein the amount of time is shorter for the standby after the I/O command. 
     
     
       14. The system of  claim 9 , wherein the timer is part of the multiple memory dies, where each die includes a separate standby timer. 
     
     
       15. The system of  claim 9 , further comprising a storage controller to manage access to the multiple memory dies, wherein the storage controller is to control selective transition of the memory dies from the standby state to the deep power down state. 
     
     
       16. The system of  claim 9 , wherein for standby after a program command, the timer is to track the standby time only if a program operation is verified for the program command. 
     
     
       17. The system of  claim 9 , wherein the amount of time comprises at least five times a read time for the memory die. 
     
     
       18. The system of  claim 9 , further comprising one or more of:
 a host processor device coupled to the multiple dies; 
 a display communicatively coupled to a host processor; 
 a network interface communicatively coupled to a host processor; or 
 a battery to power the system. 
 
     
     
       19. A nonvolatile memory device comprising:
 a memory die having nonvolatile memory cells, where the memory die is ready to receive an access command to execute; and 
 power gating circuitry to selectively transition the memory die from a standby state to a deep power down state, where the memory die is to ignore all access commands, in response to a trigger from a timer, the timer to track a standby time in response to entry of the memory die into the standby state, the timer to trigger the transition to the deep power down state based on an amount of time in the standby state, wherein:
 the amount of time is different for a standby state after an array command than for a standby after an I/O (input/output) command. 
 
 
     
     
       20. The nonvolatile memory device of  claim 19 , wherein a storage controller to control multiple memory dies controls selective transition by the power gating circuitry. 
     
     
       21. The nonvolatile memory device of  claim 19 , wherein the amount of time is shorter for the standby after the I/O command.