Inventor
DE VIVEK K
US189 patents
Patents
50 patentsUS7061806B2Jun 13, 2006
Floating-body memory cell write
INTEL CORP151 citations99
US6721222B2Apr 13, 2004
Noise suppression for open bit line DRAM architectures
INTEL CORP169 citations99
US6421269B1Jul 16, 2002
Low-leakage MOS planar capacitors for use within DRAM storage cells
INTEL CORP147 citations99
US6359802B1Mar 19, 2002
One-transistor and one-capacitor DRAM cell for logic process technology
INTEL CORP187 citations99
US6218895B1Apr 17, 2001
Multiple well transistor circuits having forward body bias
INTEL CORP293 citations99
US6218892B1Apr 17, 2001
Differential circuits employing forward body bias
INTEL CORP249 citations99
US7230846B2Jun 12, 2007
Purge-based floating body memory
INTEL CORP118 citations98
US7102951B2Sep 5, 2006
OTP antifuse cell and cell array
INTEL CORP86 citations98
US6917237B1Jul 12, 2005
Temperature dependent regulation of threshold voltage
INTEL CORP158 citations98
US6744301B1Jun 1, 2004
System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
INTEL CORP72 citations98
US6593799B2Jul 15, 2003
Circuit including forward body bias from supply voltage and ground nodes
INTEL CORP88 citations98
US6484265B2Nov 19, 2002
Software control of transistor body bias in controlling chip parameters
INTEL CORP132 citations98
US6411156B1Jun 25, 2002
Employing transistor body bias in controlling chip parameters
INTEL CORP97 citations98
US6329874B1Dec 11, 2001
Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
INTEL CORP132 citations98
US6169419B1Jan 2, 2001
Method and apparatus for reducing standby leakage current using a transistor stack effect
INTEL CORP90 citations98
US7015741B2Mar 21, 2006
Adaptive body bias for clock skew compensation
INTEL CORP134 citations97
US7020041B2Mar 28, 2006
Method and apparatus to clamp SRAM supply voltage
INTEL CORP43 citations96
US6784722B2Aug 31, 2004
Wide-range local bias generator for body bias grid
INTEL CORP58 citations96
US6519176B1Feb 11, 2003
Dual threshold SRAM cell for single-ended sensing
INTEL CORP57 citations96
US6433624B1Aug 13, 2002
Threshold voltage generation circuit
INTEL CORP70 citations96
US6300819B1Oct 9, 2001
Circuit including forward body bias from supply voltage and ground nodes
INTEL CORP53 citations96
US6272666B1Aug 7, 2001
Transistor group mismatch detection and reduction
INTEL CORP66 citations96
US6232827B1May 15, 2001
Transistors providing desired threshold voltage and reduced short channel effects with forward body bias
INTEL CORP57 citations96
US6181608B1Jan 30, 2001
Dual Vt SRAM cell with bitline leakage control
INTEL CORP62 citations96
US6100751AAug 8, 2000
Forward body biased field effect transistor providing decoupling capacitance
INTEL CORP72 citations96
US6429726B1Aug 6, 2002
Robust forward body bias generation circuit with digital trimming for DC power supply variation
INTEL CORP59 citations95
US6448840B2Sep 10, 2002
Adaptive body biasing circuit and method
INTEL CORP63 citations94
US7403426B2Jul 22, 2008
Memory with dynamically adjustable supply
INTEL CORP36 citations93
US7391640B2Jun 24, 2008
2-transistor floating-body dram
INTEL CORP45 citations93
US7342845B2Mar 11, 2008
Method and apparatus to clamp SRAM supply voltage
INTEL CORP21 citations93
US7315463B2Jan 1, 2008
Apparatus and method for multi-phase transformers
INTEL CORP44 citations93
US7307899B2Dec 11, 2007
Reducing power consumption in integrated circuits
INTEL CORP36 citations93
US7280425B2Oct 9, 2007
Dual gate oxide one time programmable (OTP) antifuse cell
INTEL CORP32 citations93
US7274181B2Sep 25, 2007
Systems, multiphase power converters with droop-control circuitry and methods
INTEL CORP24 citations93
US7167397B2Jan 23, 2007
Apparatus and method for programming a memory array
INTEL CORP50 citations93
US7123500B2Oct 17, 2006
1P1N 2T gain cell
INTEL CORP30 citations93
US7098507B2Aug 29, 2006
Floating-body dynamic random access memory and method of fabrication in tri-gate technology
INTEL CORP32 citations93
US6831871B2Dec 14, 2004
Stable memory cell read
INTEL CORP21 citations93
US6707708B1Mar 16, 2004
Static random access memory with symmetric leakage-compensated bit line
INTEL CORP46 citations93
US6643199B1Nov 4, 2003
Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports
INTEL CORP39 citations93
US6608513B2Aug 19, 2003
Flip-flop circuit having dual-edge triggered pulse generator
INTEL CORP50 citations93
US6608786B2Aug 19, 2003
Apparatus and method for a memory storage cell leakage cancellation scheme
INTEL CORP18 citations93
US6518833B2Feb 11, 2003
Low voltage PVT insensitive MOSFET based voltage reference circuit
INTEL CORP21 citations93
US6515513B2Feb 4, 2003
Reducing leakage currents in integrated circuits
INTEL CORP25 citations93
US6496402B1Dec 17, 2002
Noise suppression for open bit line DRAM architectures
INTEL CORP16 citations93
US6486706B2Nov 26, 2002
Domino logic with low-threshold NMOS pull-up
INTEL CORP36 citations93
US6366156B1Apr 2, 2002
Forward body bias voltage generation systems
INTEL CORP43 citations93
US6275071B1Aug 14, 2001
Domino logic circuit and method
INTEL CORP23 citations93
US6191606B1Feb 20, 2001
Method and apparatus for reducing standby leakage current using input vector activation
INTEL CORP42 citations93
US6177788B1Jan 23, 2001
Nonlinear body effect compensated MOSFET voltage reference
INTEL CORP22 citations93
Showing the top 50 of 189 patents by PatentIndex Score.