Inventor

YU HSIU-MEI

TW28 patents

⚠️ This page may combine multiple inventors who share the name “YU HSIU-MEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU HSIU-MEI

TAIWAN SEMICONDUCTOR MFG

Back end integrated WLCSP structure without aluminum pads

Elastomer plating mask sealed wafer level package method

Method for forming high reliability bump structure

Methods of dicing a semiconductor structure

Method to achieve robust solder bump height

Cavity structure for semiconductor structures

Method and apparatus for pretreating a substrate prior to electroplating

Method of making a bump on a substrate without ribbon residue

Method for improving a solder bump adhesion bond to a UBM contact layer

Diffusion region routing for narrow scribe-line devices

Method to reduce UBM undercut

Method and apparatus for pretreating a substrate prior to electroplating

Electrical connection for chip scale packaging

Method and apparatus for polymer dielectric surface recovery by ion implantation

Method of fine pitch bump stripping

VANGUARD INT SEMICONDUCT CORP

Method of forming dice and structure of die

High-efficiency packaged chip structure and electronic device including the same

Method of forming dice and structure of die

Semiconductor device and method forming the same

Semiconductor structure and manufacturing method of the same

Package structure and method for manufacturing the same

TAIWAN SEMICONDUCTOR MFG CO LTD

Chip package with thermal dissipation structure and method for forming the same

Semiconductor structure and manufacturing method thereof

Electrical connection for chip scale packaging

Interconnect structure and manufacturing method thereof

IND TECH RES INST

Composite bump structure and methods of fabrication

YEW MING-CHIH

Electrical connection for chip scale packaging

HSIEH MING-CHANG

Diffusion region routing for narrow scribe-line devices