Method of forming dice and structure of die

Abstract

A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

What is claimed is: 
     
       1. A method of forming a plurality of dice, comprising:
 providing a wafer structure comprising at least two die regions and at least one scribe line region disposed between the at least two die regions, wherein each of the at least two die regions comprises a high electron mobility transistor disposed therein, and the wafer structure further comprising:
 a substrate; 
 a stack of semiconductor layers disposed on the substrate, wherein the stack of the semiconductor layers is disposed in the at least two die regions and the at least one scribe line region; and 
 a component layer, disposed on the stack of semiconductor layers, wherein the component layer comprises a gate electrode, a source electrode, a drain electrode, a plug, an interconnect and a dielectric layer; 
 
 performing a laser grooving process to remove the substrate, the stack of the semiconductor layers and the component layer in the scribe line region to form at least one groove in the substrate; 
 thinning the substrate to obtain the substrate with a reduced thickness after the at least one groove is formed; and 
 performing a separation process on the substrate with the reduced thickness, wherein after performing the separation process, the reduced thickness of the substrate is remained. 
 
     
     
       2. The method of forming the plurality of dice according to  claim 1 , wherein the substrate is a ceramic substrate comprising aluminum nitride, silicon carbide, aluminum oxide, or a combination thereof. 
     
     
       3. The method of forming the plurality of dice according to  claim 1 , wherein the mechanical strength of the substrate is greater than 340 MPa. 
     
     
       4. The method of forming the plurality of dice according to  claim 1 , wherein the stack of the semiconductor layers comprises a plurality of III-V semiconductor sublayers, and the composition of each of the III-V semiconductor sublayers comprises gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), or a combination thereof. 
     
     
       5. The method of forming the plurality of dice according to  claim 1 , wherein the stack of the semiconductor layers comprises a buffer layer and a stress layer disposed on the buffer layer. 
     
     
       6. The method of forming the plurality of dice according to  claim 1 , wherein the ratio of a depth of the at least one groove to a thickness of the substrate is from 0.001 to 0.06 when the step of performing the laser grooving process is completed. 
     
     
       7. The method of forming the plurality of dice according to  claim 1 , wherein the step of forming the at least one groove further comprises: performing a mechanical sawing process on the at least one groove after the step of performing the laser grooving process. 
     
     
       8. The method of forming the plurality of dice according to  claim 1 , wherein the step of thinning the substrate comprises performing a grinding process. 
     
     
       9. The method of forming the plurality of dice according to  claim 1 , wherein the step of performing the separation process on the substrate with the reduced thickness comprises performing a cleaving process or a mechanical sawing process. 
     
     
       10. The method of forming the plurality of dice according to  claim 1 , further comprising performing a grinding process on the substrate, and the grinding process comprises: thinning the substrate and the step of performing the separation process on the substrate with the reduced thickness. 
     
     
       11. The method of forming the plurality of dice according to  claim 1 , wherein the step of providing the wafer structure comprises:
 providing the substrate; 
 forming the stack of the semiconductor layers on the substrate at a processing temperature greater than 500° C.; and 
 placing the substrate in an environment at a temperature of 25° C. to 30° C. after the step of forming the stack of the semiconductor layers on the substrate. 
 
     
     
       12. The method of forming the plurality of dice according to  claim 1 , wherein, after performing the separation process, a portion of the sidewall of the substrate comprises a first steepness formed by the separation process, and a portion of the sidewall of the stack of the semiconductor layers comprises a second steepness formed by the laser grooving process, wherein the first steepness is greater than the second steepness. 
     
     
       13. The method of forming the plurality of dice according to  claim 1 , wherein the substrate having a first thickness, the stack of the semiconductor layers having a second thickness, the first thickness is less than 250 μm, and the second thickness is from 1 μm to 25 μm. 
     
     
       14. The method of forming the plurality of dice according to  claim 13 , wherein a ratio of the second thickness to the first thickness is from 0.004 to 0.5. 
     
     
       15. The method of forming the plurality of dice according to  claim 1 , wherein performing the laser grooving process simultaneously removes the substrate, the stack of the semiconductor layers and the component layer to form the at least one groove, and a sidewall of the at least one groove in the substrate, the stack of the semiconductor layers and the component layer has the same steepness.