Inventor

ZHENG JIA ZHEN

SG89 patents

⚠️ This page may combine multiple inventors who share the name “ZHENG JIA ZHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHENG JIA ZHEN

CHARTERED SEMICONDUCTOR MFG

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method of manufacturing copper interconnect with top barrier layer

Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth

Method for forming L-shaped spacers with precise width control

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Method to form a self-aligned CMOS inverter using vertical device integration

Method of fabricating variable length vertical transistors

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer

Method for shallow trench isolation

Horizontal TRAM and method for the fabrication thereof

Method of forming a surface coating layer within an opening within a body by atomic layer deposition

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Copper interconnect with top barrier layer

Apparatus and method for planarization of spin-on materials

Method of planarization of an intermetal dielectric layer using chemical mechanical polishing

Barrier layer

Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof

Method to fill a trench and tunnel by using ALD seed layer and electroless plating

High K artificial lattices for capacitor applications to use in CU or AL BEOL

Method of forming a high performance and low cost CMOS device

Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape

Triple gate oxide process with high-k gate dielectric

Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide

Method of forming MOS/CMOS devices with dual or triple gate oxide

Method of fabricating CMOS device with dual gate electrode

Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop

Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization

Gap filling process in integrated circuits using low dielectric constant materials

Method to form elevated source/drain using poly spacer

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier layer for high density plasma chemical vapor deposited (HDP-CVD) dielectric layer

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Method to fabricate a single gate with dual work-functions

Forming dual gate oxide thickness on vertical transistors by ion implantation

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate

Method to form a recessed source drain on a trench side wall with a replacement gate technique

Ultra-thin gate oxide through post decoupled plasma nitridation anneal

Thyristor-based SRAM

Method of fabricating CMOS device with dual gate electrode

Method for reducing microloading in an etchback of spin-on-glass or polymer

CHARTERED SEMICONDUCTOR MFG CO

Method to form gate oxides of different thicknesses on a silicon substrate