Inventor

WU YUNG-HSU

TW55 patents

⚠️ This page may combine multiple inventors who share the name “WU YUNG-HSU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU YUNG-HSU

TAIWAN SEMICONDUCTOR MFG CO LTD

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Lithography using high selectivity spacers for pitch reduction

Method of fabricating semiconductor device with reduced trench distortions

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Lithography using high selectivity spacers for pitch reduction

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Self-aligned double spacer patterning process

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Method of forming trench cut

Method of forming an interconnect structure for a semiconductor device

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Structure and formation method of semiconductor device with self-aligned conductive features

Multi-metal fill with self-aligned patterning and dielectric with voids

Semiconductor device having voids and method of forming same

Method of fabricating semiconductor device with reduced trench distortions

Method of forming an interconnect structure for a semiconductor device

Trench formation using horn shaped spacer

Self-aligned double spacer patterning process

Semiconductor arrangement and formation thereof

Barrier-less structures

Using a self-assembly layer to facilitate selective formation of an etching stop layer

Barrier-less structures

Using a self-assembly layer to facilitate selective formation of an etching stop layer

Semiconductor device having voids and method of forming same

Method of fabricating semiconductor device

Semiconductor devices and methods of forming the same

Semiconductor device structure and methods of forming the same

Method of fabricating semiconductor device with reduced trench distortions

Semiconductor device with self-aligned conductive features

Integrated circuit interconnect structures with air gaps

Method of fabricating semiconductor device with reduced trench distortions

Multi-metal fill with self-aligned patterning and dielectric with voids

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Multi-metal fill with self-aligned patterning and dielectric with voids

Method for forming semiconductor device with self-aligned conductive features

Method of fabricating semiconductor device with reduced trench distortions

Integrated circuit interconnect structures with air gaps

Spacer-damage-free etching

Method of fabricating semiconductor device with reduced trench distortions

Semiconductor device having voids and method of forming same

Spacer-damage-free etching

Metal lines for interconnect structure and method of manufacturing same

TAIWAN SEMICONDUCTOR MFG

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Self-aligned double spacer patterning process

System and method for chemical-mechanical planarization of a metal layer

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Trench formation using horn shaped spacer

Spacer-damage-free etching

WU YUNG-HSU

Dielectric protection layer as a chemical-mechanical polishing stop layer