Inventor

RAVINDRAN NIRANJAY

US49 patents

⚠️ This page may combine multiple inventors who share the name “RAVINDRAN NIRANJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAVINDRAN NIRANJAY

WESTERN DIGITAL TECH INC

Data storage device extending erasures for LDPC-type decoding

Read level tracking and optimization

Mapping for multi-state programming of memory devices

Non-binary encoding for non-volatile memory

Adjustable code rates and dynamic ECC in a data storage device

Data storage device employing embedded servo sectors for magnetic tape

Data storage device employing multi-tier coding for magnetic tape

Data storage device employing memory efficient processing of un-converged codewords

Externalizing inter-symbol interference data in a data channel

Mapping for multi-state programming of memory devices

Mapping for multi-state programming of memory devices

Multi-level cell programming using optimized multiphase mapping with balanced gray code

Read level tracking and optimization

Transformation of binary data to non-binary data for storage in non-volatile memory

Data storage device employing multi-level parity sectors for data recovery procedure

Sector metrics to estimate health of written data

Extendable parity code matrix construction and utilization in a data storage device

Preprocessing for correcting insertions and deletions in DNA data storage

Nested error correction codes for DNA data storage

Data storage device configuration using mutual information

Modulation code and ECC rate optimization using symbol context mutual information

Data read synchronization from phase modulated synchronization fields in a data storage device

Adjustable code rates and dynamic ECC in a data storage device with write verification

Multi-level cell programming using optimized multiphase mapping with balanced gray code

Read level tracking and optimization

Transformation of data to non-binary data for storage in non-volatile memories

LDPC encoding for memory cells with arbitrary number of levels

Data storage device channel encoding current data using redundancy bits generated over preceding data

Magnetic recording tape having embedded servo sectors on data tracks

Data storage device employing multi-level parity sectors for data recovery procedure

Write level optimization for non-volatile memory

Multi-level cell programming using optimized multiphase mapping with balanced Gray code

Data storage device emphasizing parity sector processing of un-converged codewords

Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter

Trained states equalizer in a read channel

Offset spiral data track format for data storage devices

Multidimensional pseudorandom binary sequence analysis for a memory device

Global variance parameter based on mutual information in a data channel

Neural network soft information detector in a read channel

Signal correction using soft information in a data channel

Channel circuit with zero force equalizer

Multi-tier error correction codes for DNA data storage

Position and risk reconstruction in shingled magnetic recording data storage devices

Multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code constructions

Non-binary decoding using tensor product transforms

Overlapping processing of data tracks

WESTERN DIGITAL TECHNOLOGIES INC

Data storage device employing dynamic track trajectories

Data storage device aborting write operation based on accumulated track squeeze metric for adjacent data track

Read level tracking and optimization