P

Inventor

CHIA CHOK J

US72 patents
⚠️ This page may combine multiple inventors who share the name “CHIA CHOK J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

42 patents
US6081997AJul 4, 2000

System and method for packaging an integrated circuit using encapsulant injection

LSI LOGIC CORP202 citations99
US5973393AOct 26, 1999

Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits

LSI LOGIC CORP169 citations99
US5886398AMar 23, 1999

Molded laminate package with integral mold gate

LSI LOGIC CORP184 citations99
US5814881ASep 29, 1998

Stacked integrated chip package and method of making same

LSI LOGIC CORP229 citations99
US5728599AMar 17, 1998

Printable superconductive leadframes for semiconductor device assembly

LSI LOGIC CORP155 citations99
US6225695B1May 1, 2001

Grooved semiconductor die for flip-chip heat sink attachment

LSI LOGIC CORP123 citations98
US5557150ASep 17, 1996

Overmolded semiconductor package

LSI LOGIC CORP106 citations98
US5435482AJul 25, 1995

Integrated circuit having a coplanar solder ball contact array

LSI LOGIC CORP145 citations98
US6002169ADec 14, 1999

Thermally enhanced tape ball grid array package

LSI LOGIC CORP114 citations96
US5989937ANov 23, 1999

Method for compensating for bottom warpage of a BGA integrated circuit

LSI LOGIC CORP42 citations96
US5923047AJul 13, 1999

Semiconductor die having sacrificial bond pads for die test

LSI LOGIC CORP78 citations96
US5841191ANov 24, 1998

Ball grid array package employing raised metal contact rings

LSI LOGIC CORP58 citations96
US5745986AMay 5, 1998

Method of planarizing an array of plastically deformable contacts on an integrated circuit package to compensate for surface warpage

LSI LOGIC CORP65 citations96
US5744084AApr 28, 1998

Method of improving molding of an overmolded package body on a substrate

LSI LOGIC CORP54 citations96
US5563446AOct 8, 1996

Surface mount peripheral leaded and ball grid array package

LSI LOGIC CORP39 citations96
US5434750AJul 18, 1995

Partially-molded, PCB chip carrier package for certain non-square die shapes

LSI LOGIC CORP68 citations96
US5262927ANov 16, 1993

Partially-molded, PCB chip carrier package

LSI LOGIC CORP85 citations96
US5197183AMar 30, 1993

Modified lead frame for reducing wire wash in transfer molding of IC packages

LSI LOGIC CORP107 citations96
US5933710AAug 3, 1999

Method of providing electrical connection between an integrated circuit die and a printed circuit board

LSI LOGIC CORP26 citations93
US5643835AJul 1, 1997

Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs

LSI LOGIC CORP41 citations93
US5594626AJan 14, 1997

Partially-molded, PCB chip carrier package for certain non-square die shapes

LSI LOGIC CORP43 citations93
US5521427AMay 28, 1996

Printed wiring board mounted semiconductor device having leadframe with alignment feature

LSI LOGIC CORP36 citations93
US6519844B1Feb 18, 2003

Overmold integrated circuit package

LSI LOGIC CORP36 citations92
US6306751B1Oct 23, 2001

Apparatus and method for improving ball joints in semiconductor packages

LSI LOGIC CORP27 citations92
US6114189ASep 5, 2000

Molded array integrated circuit package

LSI LOGIC CORP51 citations92
US6088914AJul 18, 2000

Method for planarizing an array of solder balls

LSI LOGIC CORP30 citations92
US6054767AApr 25, 2000

Programmable substrate for array-type packages

LSI LOGIC CORP26 citations92
US5927505AJul 27, 1999

Overmolded package body on a substrate

LSI LOGIC CORP26 citations92
US5869889AFeb 9, 1999

Thin power tape ball grid array package

LSI LOGIC CORP43 citations92
US5841198ANov 24, 1998

Ball grid array package employing solid core solder balls

LSI LOGIC CORP32 citations92
US5353193AOct 4, 1994

High power dissipating packages with matched heatspreader heatsink assemblies

LSI LOGIC CORP35 citations92
US5463529AOct 31, 1995

High power dissipating packages with matched heatspreader heatsink assemblies

LSI LOGIC CORP24 citations91
US6963138B2Nov 8, 2005

Dielectric stack

LSI LOGIC CORP15 citations84
US6743979B1Jun 1, 2004

Bonding pad isolation

LSI LOGIC CORP16 citations84
US6297550B1Oct 2, 2001

Bondable anodized aluminum heatspreader for semiconductor packages

LSI LOGIC CORP16 citations84
US6512293B1Jan 28, 2003

Mechanically interlocking ball grid array packages and method of making

LSI LOGIC CORP15 citations83
US5789811AAug 4, 1998

Surface mount peripheral leaded and ball grid array package

LSI LOGIC CORP15 citations82
US6525421B1Feb 25, 2003

Molded integrated circuit package

LSI LOGIC CORP18 citations79
US6429534B1Aug 6, 2002

Interposer tape for semiconductor package

LSI LOGIC CORP7 citations74
US6057594AMay 2, 2000

High power dissipating tape ball grid array package

LSI LOGIC CORP13 citations74
US6040632AMar 21, 2000

Multiple sized die

LSI LOGIC CORP11 citations74
US5981311ANov 9, 1999

Process for using a removeable plating bus layer for high density substrates

LSI LOGIC CORP8 citations74

NAT SEMICONDUCTOR CORP

5 patents
US4868349ASep 19, 1989

Plastic molded pin-grid-array power package

NAT SEMICONDUCTOR CORP86 citations96
US4778641AOct 18, 1988

Method of molding a pin grid array package

NAT SEMICONDUCTOR CORP31 citations93
US4688152AAug 18, 1987

Molded pin grid array package GPT

NAT SEMICONDUCTOR CORP48 citations93
US5270262ADec 14, 1993

O-ring package

NAT SEMICONDUCTOR CORP35 citations91
US5185653AFeb 9, 1993

O-ring package

NAT SEMICONDUCTOR CORP34 citations90

INVENSAS CORP

1 patent
US10181447B2Jan 15, 2019

3D-interconnect

INVENSAS CORP4 citations84

DESAI Kishor

1 patent
US8963310B2Feb 24, 2015

Low cost hybrid high density package

DESAI Kishor5 citations79

INVENSAS LLC

1 patent
US11929337B2Mar 12, 2024

3D-interconnect

INVENSAS LLC3 citations75

Showing the top 50 of 72 patents by PatentIndex Score.