Stacked integrated chip package and method of making same

Abstract

A single leadframe package having stacked integrated chips mounted therein provides multiple electrical functions. The leadframe package construction includes a leadframe die having a substantially smaller outer peripheral dimension than a first integrated circuit chip mounted face down thereon for supporting from below the first integrated chip without obstructing its bond pads. A second integrated circuit is supported from below in a backside to backside configuration by the first integrated circuit without obstructing the bond pads of the second integrated circuit. A plurality of substantially short conductive wires interconnect electrically the first and second integrated circuit chips with selective ones of a plurality of leadframe conductors. An encapsulating material molds the construction into the single leadframe package.

We claim: 
     
       1. A single leadframe construction, includes a plurality of leadframe conductors and a molded body member for supporting the conductors in substantially fixed positions, comprising: a leadframe die paddle;   said leadframe die paddle dimensioned to permit the die paddle to be encapsulated entirely within the molded body member and in a spaced apart manner from each individual one of the plurality of leadframe conductors;   an integrated circuit chip disposed in said molded body member includes a backface surface and a frontface surface having plurality of bonds pads disposed at about its periphery;   said integrated circuit chip dimensioned to permit the chip to be encapsulated entirely within the molded body member in a spaced apart manner from each individual one of the plurality of leadframe conductors,   said integrated circuit chip dimensioned to enable said integrated chip to be supported from below by said leadframe die paddle in frontface surface abutment without any individual one of said plurality of bond pads being obstructed by said leadframe die paddle;   another integrated circuit chip disposed in said molded body member and having a backside surface and a front side surface with another plurality of bond pads disposed at about its periphery;   said another integrated circuit chip dimensioned to permit the another chip to be encapsulated entirely within the molded body member in a spaced apart manner from each individual one of the plurality of leadframe conductors and dimensioned to be supported from below by said integrated circuit in backside to backface surface abutment so that said another plurality of bond pads are completely unobstructed by said integrated circuit and said leadframe die paddle; and   a plurality of lead wires for interconnecting selected ones of the plurality of bonds pads of said integrated circuit and said another integrated circuit with selected ones of the leadframe conductors.   
     
     
       2. A single leadframe construction according to claim 1, wherein said integrated circuit and said another integrated circuit have the same dimensions. 
     
     
       3. A single leadframe construction according to claim 1, wherein said integrated circuit and said another integrated circuit have different dimensions. 
     
     
       4. A single leadframe construction according to claim 3, wherein said integrated circuit has a greater peripheral dimension that said another integrated circuit. 
     
     
       5. A single leadframe construction according to claim 1, wherein said integrated circuit and said another integrated circuit have different electrical functions. 
     
     
       6. A single leadframe construction according to claim 1, wherein said integrated circuit and said another integrated circuit perform the same electrical functions. 
     
     
       7. A two chip leadframe package having a plurality of leadframe conductors, comprising: a small leadframe die member having a given peripheral dimension;   an integrated circuit chip mounted face down to said die member, said integrated circuit chip having another peripheral dimension greater than said given peripheral dimension to expose a plurality of integrally formed bond pads disposed at about the periphery of said integrated circuit chip;   another integrated circuit chip mounted face up to said integrated circuit chip, said another integrated circuit chip having still yet another peripheral dimension substantially corresponding to said another peripheral dimension; and   conductor means for electrically interconnecting selectively the bond pads of said integrated circuit chip and the bond pads of said another integrated circuit chip with individual ones of the plurality of leadframe conductors for implementing multiple electrical functions in a single leadframe package.   
     
     
       8. The leadframe package as in claim 7, wherein said leadframe die member is encapsulated entirely within a molded body member in a spaced apart manner from each individual one of the plurality of leadframe conductors. 
     
     
       9. The leadframe package as in claim 7, wherein said integrated chip is encapsulated entirely within a molded body member in a spaced apart manner from each individual one of the plurality of leadframe conductors. 
     
     
       10. The leadframe package as in claim 7, wherein said another integrated chip is encapsulated entirely within a molded body member in a spaced apart manner from each individual one of the plurality of leadframe conductors, and sufficiently large to be supported from below by said integrated circuit in backside to backface surface abutment so that said another plurality of bond pads are completely unobstructed by said integrated circuit and said leadframe die. 
     
     
       11. The leadframe package as in claim 7, wherein said chip and said another chip have the same dimensions. 
     
     
       12. The leadframe package as in claim 7, wherein said chip and said another chip perform different dimensions. 
     
     
       13. The leadframe package as in claim 7, wherein said chip and said another chip perform different electrical functions. 
     
     
       14. The leadframe package as in claim 7, wherein said chip and said another chip perform the same electrical functions. 
     
     
       15. An integrated circuit chip structure, comprising: a supporting member;   a first integrated circuit chip mounted to said supporting member, said first chip having a first set of bond pads; and   a second integrated circuit chip mounted to said first chip, said second chip having a second set of bond pads;   said first chip comprises a first and second side, with said first side of first chip having said first set of bond pads, wherein said first chip is dimensioned to be supported by said supporting member, and further wherein said supporting member is in abutment with said first side of said first chip without said first set of bond pads being obstructed by said supporting member; and   said second chip comprises a first and second side, with said first side of second chip having said second set of bond pads, wherein said second chip is dimensioned to be supported by said first chip, and further wherein said second side of said first chip is in abutment with said second side of said second chip.   
     
     
       16. The integrated circuit chip structure in claim 15, further comprising: a plurality of leadframe conductors; and   a plurality of lead wires electrically interconnecting said leadframe conductors to respective said first and said set of bond pads.   
     
     
       17. The integrated circuit chip structure in claim 16, wherein said supporting member, first integrated chip, second integrated chip, and plurality of said lead wires are encapsulated entirely by a molded body member. 
     
     
       18. The integrated chip structure in claim 17, wherein said first and said second chip have the same dimensions. 
     
     
       19. The integrated chip structure in claim 17, wherein said first and said second chip have different dimensions. 
     
     
       20. The integrated chip structure in claim 17, wherein said first chip is larger than said second chip. 
     
     
       21. The integrated chip structure in claim 17, wherein said first chip and said second chip perform different electrical functions. 
     
     
       22. The integrated chip structure in claim 17, wherein said first chip and said second chip perform the same electrical functions. 
     
     
       23. The integrated chip structure in claim 17, wherein said supporting member is a leadframe die paddle.