P

Inventor

LOW QWAI H

US42 patents
⚠️ This page may combine multiple inventors who share the name “LOW QWAI H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

28 patents
US5973393AOct 26, 1999

Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits

LSI LOGIC CORP169 citations99
US5886398AMar 23, 1999

Molded laminate package with integral mold gate

LSI LOGIC CORP184 citations99
US5814881ASep 29, 1998

Stacked integrated chip package and method of making same

LSI LOGIC CORP229 citations99
US5923047AJul 13, 1999

Semiconductor die having sacrificial bond pads for die test

LSI LOGIC CORP78 citations96
US5841191ANov 24, 1998

Ball grid array package employing raised metal contact rings

LSI LOGIC CORP58 citations96
US6798035B1Sep 28, 2004

Bonding pad for low k dielectric

LSI LOGIC CORP20 citations92
US6114189ASep 5, 2000

Molded array integrated circuit package

LSI LOGIC CORP51 citations92
US5353193AOct 4, 1994

High power dissipating packages with matched heatspreader heatsink assemblies

LSI LOGIC CORP35 citations92
US5463529AOct 31, 1995

High power dissipating packages with matched heatspreader heatsink assemblies

LSI LOGIC CORP24 citations91
US6329278B1Dec 11, 2001

Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads

LSI LOGIC CORP40 citations90
US6963138B2Nov 8, 2005

Dielectric stack

LSI LOGIC CORP15 citations84
US6743979B1Jun 1, 2004

Bonding pad isolation

LSI LOGIC CORP16 citations84
US6825563B1Nov 30, 2004

Slotted bonding pad

LSI LOGIC CORP17 citations82
US6573113B1Jun 3, 2003

Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads

LSI LOGIC CORP13 citations79
US6429534B1Aug 6, 2002

Interposer tape for semiconductor package

LSI LOGIC CORP7 citations74
US6057594AMay 2, 2000

High power dissipating tape ball grid array package

LSI LOGIC CORP13 citations74
US6040632AMar 21, 2000

Multiple sized die

LSI LOGIC CORP11 citations74
US5568683AOct 29, 1996

Method of cooling a packaged electronic device

LSI LOGIC CORP8 citations72
US5386144AJan 31, 1995

Snap on heat sink attachment

LSI LOGIC CORP14 citations70
US6489571B1Dec 3, 2002

Molded tape ball grid array package

LSI LOGIC CORP3 citations63
US6143586ANov 7, 2000

Electrostatic protected substrate

LSI LOGIC CORP5 citations63
US5973397AOct 26, 1999

Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density

LSI LOGIC CORP3 citations63
US6998638B2Feb 14, 2006

Test structure for detecting bonding-induced cracks

LSI LOGIC CORP2 citations62
US6781150B2Aug 24, 2004

Test structure for detecting bonding-induced cracks

LSI LOGIC CORP4 citations62
US6861748B2Mar 1, 2005

Test structure

LSI LOGIC CORP2 citations60
US6486002B1Nov 26, 2002

Tape design to reduce warpage

LSI LOGIC CORP1 citations49
US6603200B1Aug 5, 2003

Integrated circuit package

LSI LOGIC CORP1 citations48
US6425179B1Jul 30, 2002

Method for assembling tape ball grid arrays

LSI LOGIC CORP0 citations42

LSI CORP

3 patents

INVENSAS CORP

2 patents

TESSERA INC

2 patents

LOW QWAI H

2 patents

DESAI Kishor

1 patent

INVENSAS LLC

1 patent

ADEIA SEMICONDUCTOR TECH LLC

1 patent

LOHR MITCHEL E

1 patent

(unassigned)

1 patent