P

Inventor

VOOGEL MARTIN L

US49 patents

Patents

49 patents
US6208549B1Mar 27, 2001

One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS

XILINX INC98 citations98
US5880620AMar 9, 1999

Pass gate circuit with body bias control

XILINX INC253 citations98
US6768338B1Jul 27, 2004

PLD lookup table including transistors of more than one oxide thickness

XILINX INC62 citations96
US6281696B1Aug 28, 2001

Method and test circuit for developing integrated circuit fabrication processes

XILINX INC65 citations96
US6157213ADec 5, 2000

Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip

XILINX INC65 citations96
US6044012AMar 28, 2000

Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process

XILINX INC81 citations96
US7400123B1Jul 15, 2008

Voltage regulator with variable drive strength for improved phase margin in integrated circuits

XILINX INC29 citations93
US7110281B1Sep 19, 2006

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

XILINX INC26 citations93
US7064574B1Jun 20, 2006

PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets

XILINX INC28 citations93
US6949951B1Sep 27, 2005

Integrated circuit multiplexer including transistors of more than one oxide thickness

XILINX INC21 citations93
US6768335B1Jul 27, 2004

Integrated circuit multiplexer including transistors of more than one oxide thickness

XILINX INC21 citations93
US6243294B1Jun 5, 2001

Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process

XILINX INC25 citations93
US6055205AApr 25, 2000

Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process

XILINX INC42 citations93
US5959821ASep 28, 1999

Triple-well silicon controlled rectifier with dynamic holding voltage

XILINX INC38 citations93
US5949712ASep 7, 1999

Non-volatile memory array using gate breakdown structure

XILINX INC48 citations93
US5835402ANov 10, 1998

Non-volatile storage for standard CMOS integrated circuits

XILINX INC47 citations93
US7283409B1Oct 16, 2007

Data monitoring for single event upset in a programmable logic device

XILINX INC22 citations92
US7109783B1Sep 19, 2006

Method and apparatus for voltage regulation within an integrated circuit

XILINX INC20 citations92
US6822894B1Nov 23, 2004

Single event upset in SRAM cells in FPGAs with leaky gate transistors

XILINX INC48 citations92
US6753722B1Jun 22, 2004

Method and apparatus for voltage regulation within an integrated circuit

XILINX INC27 citations92
US6549458B1Apr 15, 2003

Non-volatile memory array using gate breakdown structures

XILINX INC25 citations92
US6522582B1Feb 18, 2003

Non-volatile memory array using gate breakdown structures

XILINX INC20 citations92
US7504877B1Mar 17, 2009

Charge pump and voltage regulator for body bias voltage

XILINX INC26 citations91
US7907461B1Mar 15, 2011

Structures and methods of preventing an unintentional state change in a data storage node of a latch

XILINX INC22 citations89
US7859918B1Dec 28, 2010

Method and apparatus for trimming die-to-die variation of an on-chip generated voltage reference

XILINX INC22 citations86
US10963411B1Mar 30, 2021

Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture

XILINX INC8 citations84
US7385416B1Jun 10, 2008

Circuits and methods of implementing flip-flops in dual-output lookup tables

XILINX INC15 citations84
US7301796B1Nov 27, 2007

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

XILINX INC10 citations84
US7239173B1Jul 3, 2007

Programmable memory element with power save mode in a programmable logic device

XILINX INC14 citations84
US7053654B1May 30, 2006

PLD lookup table including transistors of more than one oxide thickness

XILINX INC12 citations84
US6982451B1Jan 3, 2006

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

XILINX INC15 citations84
US6438065B1Aug 20, 2002

Redundancy architecture and method for non-volatile storage

XILINX INC14 citations84
US11043484B1Jun 22, 2021

Method and apparatus of package enabled ESD protection

XILINX INC8 citations83
US7119570B1Oct 10, 2006

Method of measuring performance of a semiconductor device and circuit for the same

XILINX INC14 citations83
US6509739B1Jan 21, 2003

Method for locating defects and measuring resistance in a test structure

XILINX INC15 citations81
US6621289B1Sep 16, 2003

Method and test circuit for developing integrated circuit fabrication processes

XILINX INC11 citations74
US6362651B1Mar 26, 2002

Method for fabricating PLDs including multiple discrete devices formed on a single chip

XILINX INC10 citations74
US6137714AOct 24, 2000

Dynamic memory cell for a programmable logic device

XILINX INC13 citations74
US5986958ANov 16, 1999

DRAM configuration in PLDs

XILINX INC10 citations74
US11270977B2Mar 8, 2022

Power delivery network for active-on-active stacked integrated circuits

XILINX INC4 citations73
US10726181B1Jul 28, 2020

Regularity of fabrics in programmable logic devices

XILINX INC3 citations73
US9882562B1Jan 30, 2018

Rotated integrated circuit die and chip packages having the same

XILINX INC6 citations73
US7109746B1Sep 19, 2006

Data monitoring for single event upset in a programmable logic device

XILINX INC8 citations73
US7378869B1May 27, 2008

Lookup table circuits programmable to implement flip-flops

XILINX INC3 citations63
US7376000B1May 20, 2008

Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets

XILINX INC1 citations63
US7452765B1Nov 18, 2008

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

XILINX INC3 citations62
US6033938AMar 7, 2000

Antifuse with improved on-state reliability

XILINX INC5 citations62
US11428733B1Aug 30, 2022

On-die virtual probes (ODVP) for integrated circuitries

XILINX INC0 citations61
US11652481B2May 16, 2023

Designing single event upset latches

XILINX INC1 citations58