Inventor · disambiguated record
Mack W. Riley
Also filed as: RILEY MACK · RILEY MACK W · RILEY MACK WAYNE
44 granted patents·11 pending applications·298 citations·filing 1986–2018
98Inventor score
Top patents by PatentIndex Score
55 records- 0191US7496692B2Validating chip configuration dataIBM·Filed 2005·Granted Feb 24, 2009·30 cites·10 claims
- 0288US7484153B2Systems and methods for LBIST testing using isolatable scan chainsTOSHIBA KK·Filed 2005·Granted Jan 27, 2009·17 cites·8 claims
- 0387US7500164B2Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologiesIBM·Filed 2006·Granted Mar 3, 2009·18 cites·1 claims
- 0484US7308598B2Algorithm to encode and compress array redundancy dataIBM·Filed 2004·Granted Dec 11, 2007·38 cites·18 claims
- 0579US9057766B2Isolating failing latches using a logic built-in self-testIBM·Filed 2012·Granted Jun 16, 2015·5 cites·20 claims
- 0679US8943377B2On-chip detection of types of operations tested by an LBISTHARPER MICHAEL W·Filed 2012·Granted Jan 27, 2015·7 cites·10 claims
- 0778US7702944B2Dynamic frequency scaling sequence for multi-gigahertz microprocessorsIBM·Filed 2009·Granted Apr 20, 2010·7 cites·5 claims
- 0877US7373573B2Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testingIBM·Filed 2005·Granted May 13, 2008·9 cites·8 claims
- 0976US7895426B2Secure power-on reset engineIBM·Filed 2007·Granted Feb 22, 2011·8 cites·20 claims
- 1076US7512925B2System and method for reducing test time for loading and executing an architecture verification program for a SoCIBM·Filed 2006·Granted Mar 31, 2009·11 cites·20 claims
- 1175US9250645B2Circuit design for balanced logic stressIBM·Filed 2014·Granted Feb 2, 2016·3 cites·12 claims
- 1275US7492793B2Method for controlling asynchronous clock domains to perform synchronous operationsIBM·Filed 2005·Granted Feb 17, 2009·5 cites·1 claims
- 1374US7610531B2Modifying a test pattern to control power supply noiseIBM·Filed 2006·Granted Oct 27, 2009·7 cites·21 claims
- 1474US7546504B2System and method for advanced logic built-in self test with selection of scan channelsIBM·Filed 2006·Granted Jun 9, 2009·7 cites·17 claims
- 1573US7711875B2High speed on-chip serial link apparatusIBM·Filed 2008·Granted May 4, 2010·5 cites·14 claims
- 1670US10608763B2Built-in self-test for receiver channelIBM·Filed 2018·Granted Mar 31, 2020·2 cites·20 claims
- 1769US9128150B2On-chip detection of types of operations tested by an LBISTIBM·Filed 2013·Granted Sep 8, 2015·2 cites·10 claims
- 1869US8027798B2Digital thermal sensor test implementation without using main core voltage supplyIBM·Filed 2007·Granted Sep 27, 2011·7 cites·21 claims
- 1968US7698608B2Using a single bank of efuses to successively store testing data from multiple stages of testingIBM·Filed 2007·Granted Apr 13, 2010·5 cites·12 claims
- 2067US7430624B2High speed on-chip serial link apparatus and methodIBM·Filed 2005·Granted Sep 30, 2008·3 cites·6 claims
- 2167US7350096B2Circuit to reduce power supply fluctuations in high frequency/ high power circuitsIBM·Filed 2004·Granted Mar 25, 2008·10 cites·4 claims
- 2266US7620126B2Method and apparatus for detecting frequency lock in a system including a frequency synthesizerIBM·Filed 2005·Granted Nov 17, 2009·6 cites·14 claims
- 2364US7809974B2Circuit to reduce power supply fluctuations in high frequency/high power circuitsIBM·Filed 2008·Granted Oct 5, 2010·2 cites·13 claims
- 2464US7478300B2Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit deviceIBM·Filed 2006·Granted Jan 13, 2009·4 cites·1 claims
- 2562US7434127B2eFuse programming data alignment verification apparatus and methodIBM·Filed 2005·Granted Oct 7, 2008·4 cites·15 claims
- 2661US9336105B2Evaluation of multiple input signature register resultsRILEY MACK WAYNE·Filed 2010·Granted May 10, 2016·2 cites·24 claims
- 2761US7627771B2Clock control hierarchy for integrated microprocessors and systems-on-a-chipIBM·Filed 2005·Granted Dec 1, 2009·2 cites·20 claims
- 2860US7562272B2Apparatus and method for using eFuses to store PLL configuration dataIBM·Filed 2005·Granted Jul 14, 2009·4 cites·1 claims
- 2959US5301279AApparatus for conditioning priority arbitrationIBM·Filed 1992·Granted Apr 5, 1994·33 cites·14 claims
- 3058US7430264B2Method to reduce transient current swings during mode transitions of high frequency/high power chipsIBM·Filed 2004·Granted Sep 30, 2008·7 cites·10 claims
- 3157US7688930B2Using eFuses to store PLL configuration dataIBM·Filed 2008·Granted Mar 30, 2010·3 cites·14 claims
- 3256US7908536B2Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit deviceIBM·Filed 2008·Granted Mar 15, 2011·2 cites·17 claims
- 3356US7656237B2Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logicIBM·Filed 2004·Granted Feb 2, 2010·4 cites·19 claims
- 3455US9383767B2Circuit design for balanced logic stressIBM·Filed 2014·Granted Jul 5, 2016·0 cites·5 claims
- 3554US7792154B2Controlling asynchronous clock domains to perform synchronous operationsIBM·Filed 2008·Granted Sep 7, 2010·0 cites·1 claims
- 3652US8144689B2Controlling asynchronous clock domains to perform synchronous operationsCHELSTROM NATHAN P·Filed 2008·Granted Mar 27, 2012·1 cites·17 claims
- 3751US7831006B2Circuit to reduce transient current swings during mode transitions of high frequency/high power chipsIBM·Filed 2008·Granted Nov 9, 2010·0 cites·10 claims
- 3850US8943458B1Determining chip burn-in workload using emulated application conditionIBM·Filed 2013·Granted Jan 27, 2015·0 cites·20 claims
- 3950US7516350B2Dynamic frequency scaling sequence for multi-gigahertz microprocessorsIBM·Filed 2004·Granted Apr 7, 2009·3 cites·4 claims
- 4050US7284138B2Deep power saving by disabling clock distribution without separate clock distribution for power management logicIBM·Filed 2004·Granted Oct 16, 2007·1 cites·6 claims
- 4150US4691170AFrequency multiplier circuitIBM·Filed 1986·Granted Sep 1, 1987·14 cites·16 claims
- 4247US8639855B2Information collection and storage for single core chips to 'N core chipsHARPER MICHAEL W·Filed 2008·Granted Jan 28, 2014·0 cites·19 claims
- 4344US7590194B2Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizerIBM·Filed 2005·Granted Sep 15, 2009·0 cites·7 claims
- 4443US2007174679A1Method and apparatus for processing error information and injecting errors in a processor systemIBM·Filed 2006·Application pending·0 cites
- 4542US7721168B2eFuse programming data alignment verificationIBM·Filed 2008·Granted May 18, 2010·0 cites·17 claims
- 4640US2009222251A1Structure For An Integrated Circuit That Employs Multiple InterfacesIBM·Filed 2008·Application pending·0 cites
- 4739US2008159010A1Multi-use eFuse MacroGORDON TARL S·Filed 2008·Application pending·0 cites
- 4838US2009089636A1Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core ProcessorsFERNSLER MATTHEW E·Filed 2007·Application pending·0 cites
- 4937US2009121747A1Maintaining Circuit Delay Characteristics During Power Management ModeDHONG SANG HOO·Filed 2007·Application pending·0 cites
- 5037US2006080583A1Store scan data in trace arrays for on-board software accessIBM·Filed 2004·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
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