Inventor
ZIMMER VINCENT
US58 patents
⚠️ This page may combine multiple inventors who share the name “ZIMMER VINCENT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
41 patentsUS7594124B2Sep 22, 2009
Cross validation of data using multiple subsystems
INTEL CORP41 citations96
US11570264B1Jan 31, 2023
Provenance audit trails for microservices architectures
INTEL CORP15 citations94
US7366891B2Apr 29, 2008
Methods and apparatus to provide dual-mode drivers in processor systems
INTEL CORP20 citations93
US6633964B2Oct 14, 2003
Method and system using a virtual lock for boot block flash
INTEL CORP26 citations93
US7934209B2Apr 26, 2011
Method for firmware variable storage with eager compression, fail-safe extraction and restart time compression scan
INTEL CORP22 citations92
US7200772B2Apr 3, 2007
Methods and apparatus to reinitiate failed processors in multiple-processor systems
INTEL CORP12 citations81
US12293182B2May 6, 2025
Firmware component with self-descriptive dependency information
INTEL CORP1 citations75
US11875147B2Jan 16, 2024
Firmware component with self-descriptive dependency information
INTEL CORP2 citations73
US11792280B2Oct 17, 2023
Provenance audit trails for microservices architectures
INTEL CORP1 citations73
US11249748B2Feb 15, 2022
Firmware component with self-descriptive dependency information
INTEL CORP3 citations73
US10761951B2Sep 1, 2020
FPGA based functional safety control logic (FFSCL)
INTEL CORP2 citations73
US10049216B2Aug 14, 2018
Media protection policy enforcement for multiple-operating-system environments
INTEL CORP2 citations73
US12079612B2Sep 3, 2024
Firmware boot task distribution to enable low latency boot performance
INTEL CORP4 citations72
US11941409B2Mar 26, 2024
Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process
INTEL CORP2 citations71
US10546156B2Jan 28, 2020
MRC training in FPGA-in-memory-controller
INTEL CORP2 citations71
US11593123B2Feb 28, 2023
Methods and apparatus for boot time reduction in a processor and programmable logic device environment
INTEL CORP2 citations69
US11074085B2Jul 27, 2021
Methods and apparatus for boot time reduction in a processor and programmable logic device environment
INTEL CORP2 citations69
US7953916B2May 31, 2011
Dynamic, local retriggered interrupt routing discovery method
INTEL CORP6 citations69
US11768691B2Sep 26, 2023
Boot process for early display initialization and visualization
INTEL CORP2 citations68
US7188238B2Mar 6, 2007
Methods and apparatus to update a basic input/output system (BIOS)
INTEL CORP7 citations68
US12393430B2Aug 19, 2025
Methods and apparatus to increase boot performance by categorizing boot tasks
INTEL CORP1 citations63
US12063280B2Aug 13, 2024
Provenance audit trails for microservices architectures
INTEL CORP0 citations62
US11870669B2Jan 9, 2024
At-scale telemetry using interactive matrix for deterministic microservices performance
INTEL CORP1 citations62
US11429496B2Aug 30, 2022
Platform data resiliency mechanism
INTEL CORP0 citations62
US8001348B2Aug 16, 2011
Method to qualify access to a block storage device via augmentation of the device's controller and firmware flow
INTEL CORP4 citations62
US10929146B2Feb 23, 2021
Dynamic timer adjustment to improve performance and inhibit livelock conditions
INTEL CORP0 citations61
US8631259B2Jan 14, 2014
Method and apparatus for quick resumption of a processing system with volatile memory
INTEL CORP1 citations61
US12379934B2Aug 5, 2025
Decoupling silicon initialization and bootloader by providing silicon initialization service
INTEL CORP0 citations60
US10635607B2Apr 28, 2020
Methods, systems and apparatus to improve boot efficiency
INTEL CORP1 citations59
US11068276B2Jul 20, 2021
Controlled customization of silicon initialization
INTEL CORP0 citations58
US12578956B2Mar 17, 2026
Method and apparatus for firmware patching
INTEL CORP0 citations56
US12124856B2Oct 22, 2024
Platform hardening for bootloaders via reference firmware
INTEL CORP0 citations56
US12481504B2Nov 25, 2025
Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention
INTEL CORP0 citations52
US12271325B2Apr 8, 2025
System management mode runtime resiliency manager
INTEL CORP0 citations52
US12217175B2Feb 4, 2025
Methods and apparatus to conditionally activate a big core in a computing system
INTEL CORP0 citations52
US11061692B2Jul 13, 2021
Low latency boot from zero-power state
INTEL CORP0 citations52
US10025934B2Jul 17, 2018
Media protection policy enforcement for multiple-operating-system environments
INTEL CORP0 citations52
US7984237B2Jul 19, 2011
Integrated circuit capable of pre-fetching data
INTEL CORP0 citations52
US9600671B2Mar 21, 2017
Systems and methods for account recovery using a platform attestation credential
INTEL CORP1 citations51
US9378371B2Jun 28, 2016
Systems and methods for account recovery using a platform attestation credential
INTEL CORP1 citations51
US9323541B2Apr 26, 2016
Method, apparatus, system, and machine readable storage medium for providing software security
INTEL CORP1 citations51
ROTHMAN MICHAEL M
1 patentTANG DI
1 patentZIMMER VINCENT
1 patentBULUSU MALLIK
1 patentSWANSON ROBERT C
1 patentYAO JIEWEN
1 patentDURHAM DAVID
1 patentDORAN MARK
1 patentSAKTHIKUMAR PALSAMY
1 patentShowing the top 50 of 58 patents by PatentIndex Score.