Inventor · disambiguated record
Geeyarpuram N. Santhanakrishnan
Also filed as: SANTHANAKRISHNAN GEEYARPURAM · SANTHANAKRISHNAN GEEYARPURAM N
13 granted patents·2 pending applications·76 citations·filing 2005–2022
90Inventor score
Files withINTEL CORP7YIGZAW THEODROS3SANTHANAKRISHNAN GEEYARPURAM N2BLANKENSHIP ROBERT G1KURTS TSVIKA1
Top patents by PatentIndex Score
15 records- 0190US8275942B2Performance prioritization in multi-threaded processorsYIGZAW THEODROS·Filed 2005·Granted Sep 25, 2012·31 cites·32 claims
- 0287US9639490B2Ring protocol for low latency interconnect switchBLANKENSHIP ROBERT G·Filed 2011·Granted May 2, 2017·13 cites·19 claims
- 0387US9575895B2Providing common caching agent for core and integrated input/output (IO) moduleINTEL CORP·Filed 2015·Granted Feb 21, 2017·5 cites·17 claims
- 0480US8984228B2Providing common caching agent for core and integrated input/output (IO) moduleLIU YEN-CHENG·Filed 2011·Granted Mar 17, 2015·5 cites·19 claims
- 0577US12189479B2Apparatus and method for detecting and recovering from data fetch errorsINTEL CORP·Filed 2022·Granted Jan 7, 2025·0 cites·25 claims
- 0675US9448879B2Apparatus and method for implement a multi-level memory hierarchyYIGZAW THEODROS·Filed 2011·Granted Sep 20, 2016·4 cites·24 claims
- 0769US2021318932A1Apparatus and method for detecting and recovering from data fetch errorsINTEL CORP·Filed 2021·Application pending·0 cites
- 0868US8079031B2Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metricSANTHANAKRISHNAN GEEYARPURAM N·Filed 2005·Granted Dec 13, 2011·7 cites·18 claims
- 0967US8347035B2Posting weakly ordered transactionsINTEL CORP·Filed 2008·Granted Jan 1, 2013·4 cites·20 claims
- 1064US11048587B2Apparatus and method for detecting and recovering from data fetch errorsINTEL CORP·Filed 2019·Granted Jun 29, 2021·0 cites·25 claims
- 1160US7353338B2Credit mechanism for multiple banks of shared cacheINTEL CORP·Filed 2005·Granted Apr 1, 2008·2 cites·30 claims
- 1257US8074131B2Generic debug external connection (GDXC) for high integration integrated circuitsKURTS TSVIKA·Filed 2009·Granted Dec 6, 2011·5 cites·22 claims
- 1353US10223204B2Apparatus and method for detecting and recovering from data fetch errorsYIGZAW THEODROS·Filed 2011·Granted Mar 5, 2019·0 cites·18 claims
- 1449US9910807B2Ring protocol for low latency interconnect switchINTEL CORP·Filed 2017·Granted Mar 6, 2018·0 cites·21 claims
- 1537US2008056230A1Opportunistic channel unblocking mechanism for ordered channels in a point-to-point interconnectSANTHANAKRISHNAN GEEYARPURAM N·Filed 2006·Application pending·0 cites
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