Apparatus and method for detecting and recovering from data fetch errors

Abstract

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

What is claimed is: 
     
         1 . A method for recovering from instruction fetch errors within a processor core, the method comprising:
 detecting an error associated with a cache line fetched from a first memory location within a memory hierarchy in response to an instruction fetch operation, the cache line containing at least part of an instruction targeted by the instruction fetch operation;   determining that the instruction fetch operation is associated with a non-speculative access and that at least part of the instruction is associated with a critical chunk of the cache line; and   responsive to the determining, performing one or more recovery operations to prevent execution of the instruction, the one or more recovery operations comprising withholding data associated with the cache line, stalling execution of the instruction, logging an instruction fetch error in an error log, and/or generating an exception signal.   
     
     
         2 . The method of  claim 1 , further comprising:
 determining that the instruction fetch operation is associated with a speculative access and responsively allowing the instruction to be executed.   
     
     
         3 . The method of  claim 2 , further comprising:
 determining that the instruction is not associated with the critical chunk of the cache line and will not be used immediately, and responsively storing the cache line in an instruction cache in a poisoned state.   
     
     
         4 . The method of  claim 3 , further comprising:
 detecting an access to the cache line in the instruction cache and responsively invalidating the cache line based, at least in part, on the poison state associated with the cache line.   
     
     
         5 . The method of  claim 4 , further comprising:
 responsive to invalidating the cache line in the instruction cache, treating the access as a cache miss and fetch the cache line from a second memory location in the memory hierarchy.   
     
     
         6 . The method of  claim 5 , wherein the second memory location is further up the memory hierarchy than the first memory location. 
     
     
         7 . The method of  claim 3 , wherein storing the cache line in the instruction cache further comprises removing the cache line from the first memory location. 
     
     
         8 . The method of  claim 1 , wherein logging the instruction fetch error in the error log further comprises storing a system address associated with the instruction fetch operation in the error log. 
     
     
         9 . An apparatus comprising:
 instruction fetch circuitry to fetch a cache line from a first memory location within a memory hierarchy in response to an instruction fetch operation; and   error processing circuitry to:
 detect an error associated with the cache line fetched from the first memory location, the cache line containing at least part of an instruction targeted by the instruction fetch operation; 
 determine that the instruction fetch operation is associated with a non-speculative access and that at least part of the instruction is associated with a critical chunk of the cache line; and 
 perform or initiate one or more recovery operations to prevent execution of the instruction, the one or more recovery operations comprising withholding data associated with the cache line, stalling execution of the instruction, logging an instruction fetch error in an error log, and/or generating an exception signal. 
   
     
     
         10 . The apparatus of  claim 9 , further comprising:
 execution circuitry to execute the instruction responsive to a determination by the error processing circuitry that the instruction fetch operation is associated with a speculative access.   
     
     
         11 . The apparatus of  claim 10 , further comprising:
 an instruction cache to store the cache line in a poisoned state responsive to a determination by the error processing circuitry that the instruction is not associated with the critical chunk of the cache line.   
     
     
         12 . The apparatus of  claim 11 , wherein the instruction cache is to detect an access to the cache line in the instruction cache and responsively invalidating the cache line based, at least in part, on the poison state associated with the cache line. 
     
     
         13 . The apparatus of  claim 12 , wherein responsive to the cache line being invalidated in the instruction cache, the instruction fetch circuitry is to treat the access as a cache miss and fetch the cache line from a second memory location in the memory hierarchy. 
     
     
         14 . The apparatus of  claim 13 , wherein the second memory location is further up the memory hierarchy than the first memory location. 
     
     
         15 . The apparatus of  claim 11 , wherein the cache line is removed from the first memory location when stored into the instruction cache. 
     
     
         16 . The apparatus of  claim 9 , further comprising:
 the error log to store the instruction fetch error in the error log with a system address associated with the instruction fetch operation.   
     
     
         17 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations of:
 detecting an error associated with a cache line fetched from a first memory location within a memory hierarchy in response to an instruction fetch operation, the cache line containing at least part of an instruction targeted by the instruction fetch operation;   determining that the instruction fetch operation is associated with a non-speculative access and that at least part of the instruction is associated with a critical chunk of the cache line; and   responsive to the determining, performing one or more recovery operations to prevent execution of the instruction, the one or more recovery operations comprising withholding data associated with the cache line, stalling execution of the instruction, logging an instruction fetch error in an error log, and/or generating an exception signal.   
     
     
         18 . The non-transitory machine-readable medium of  claim 17 , further comprising:
 determining that the instruction fetch operation is associated with a speculative access and responsively allowing the instruction to be executed.   
     
     
         19 . The non-transitory machine-readable medium of  claim 18 , further comprising:
 determining that the instruction is not associated with the critical chunk of the cache line and will not be used immediately, and responsively storing the cache line in an instruction cache in a poisoned state.   
     
     
         20 . The non-transitory machine-readable medium of  claim 19 , further comprising:
 detecting an access to the cache line in the instruction cache and responsively invalidating the cache line based, at least in part, on the poison state associated with the cache line.   
     
     
         21 . The non-transitory machine-readable medium of  claim 20 , further comprising:
 responsive to invalidating the cache line in the instruction cache, treating the access as a cache miss and fetch the cache line from a second memory location in the memory hierarchy.   
     
     
         22 . The non-transitory machine-readable medium of  claim 21 , wherein the second memory location is further up the memory hierarchy than the first memory location. 
     
     
         23 . The non-transitory machine-readable medium of  claim 19 , wherein storing the cache line in the instruction cache further comprises removing the cache line from the first memory location. 
     
     
         24 . The non-transitory machine-readable medium of  claim 17 , wherein logging the instruction fetch error in the error log further comprises storing a system address associated with the instruction fetch operation in the error log.