Inventor

CHONG YUNG FU

SG46 patents

⚠️ This page may combine multiple inventors who share the name “CHONG YUNG FU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHONG YUNG FU

CHARTERED SEMICONDUCTOR MFG

Formation of raised source/drain structures in NFET with embedded SiGe in PFET

Activating source and drain junctions and extensions using a single laser anneal

Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process

Method to form selective strained Si using lateral epitaxy

Method to engineer etch profiles in Si substrate for advanced semiconductor devices

Method of fabricating a transistor structure

Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor

Formation of silicided shallow junctions using implant through metal technology and laser annealing process

Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure

Method to reduce polysilicon depletion in MOS transistors

Method to form MOS transistors with shallow junctions using laser annealing

Incorporation of dielectric layer onto SThM tips for direct thermal analysis

Laser activation of implanted contact plug for memory bitline fabrication

Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure

Method of fabricating short channel MOS transistors with source/drain extensions

Integrated circuit system employing a condensation process

Method to fabricate elevated source/drain structures in MOS transistors

Strained channel transistor and method of fabrication thereof

Method to fabricate variable work function gates for FUSI devices

Semiconductor device and fabrication method

GLOBALFOUNDRIES SG PTE LTD

Method to control source/drain stressor profiles for stress engineering

Integrated circuit isolation system

Transistor with wrap-around extrinsic base

Transistor with wrap-around extrinsic base

Transistor with wrap-around extrinsic base

Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing

Contact via structures of semiconductor devices

Contact via structures of semiconductor devices

Air gap with inverted T-shaped lower portion extending through at least one metal layer, and related method

Methods for fabricating device substrates and integrated circuits

Transistor with source-drain silicide pullback

Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures

IBM

Method and structure to form self-aligned selective-SOI

Method of forming substantially L-shaped silicide contact for a semiconductor device

Method of manufacturing a semiconductor structure

Gate stress engineering for MOSFET

CHONG YUNG FU

Method to control source/drain stressor profiles for stress engineering

Formation of raised source/drain structures in NFET with embedded SiGe in PFET

Strained channel transistor and method of fabrication thereof

TAN SHYUE SENG

Diffusion barrier and method of formation thereof

Semiconductor system using germanium condensation

SAMSUNG ELECTRONICS CO LTD

Embedded stressor structure and process

INFINEON TECHNOLOGIES AG

Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

LUO ZHIJIONG

Substantially L-shaped silicide for contact

HAN JIN-PING

Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

UNIV NANYANG TECH

Method for forming a shallow junction region using defect engineering and laser annealing