Inventor

NARDINI LEWIS

US34 patents

⚠️ This page may combine multiple inventors who share the name “NARDINI LEWIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARDINI LEWIS

TEXAS INSTRUMENTS INC

Data processing system with register store/load utilizing data packing/unpacking

Microprocessor with instructions for shuffling and dealing data

Progressive extended compression mask for dynamic trace

Tracing through reset

Tracing program counter addresses using native program counter format and instruction count format

Systems and methods for secure debugging and profiling of a computer system

Apparatus and method for trace stream identification of a processor debug halt signal

Address range comparator for detection of multi size memory accesses with data matching qualification and full or partial overlap

Scan sequenced power-on initialization

Programmable extended compression mask for dynamic trace

Tracing through reset

Progressive extended compression mask for dynamic trace

Reporting a saturated counter value

Tracing program counter addresses using native program counter format and instruction count format

Program counter range comparator with equality, greater than, less than and non-equal detection modes

Progressive extended compression mask for dynamic trace

Tracing through reset

Programmable extended compression mask for dynamic trace

Separation of debug windows by IDS bit

Multi-port trace data handling

Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline

Pipeline stage single cycle sliding alignment correction of memory read data with integrated data reordering for load and store instructions

Token-based trace system

Reporting a saturated counter value

Programmable extended compression mask for dynamic trace

Tracing user change of program counter during stop event

Distributed power control for controlling power consumption based on detected activity of logic blocks

Program counter range comparator with equality, greater than, less than and non-equal detection modes

Multi-port trace data handling

Packet based integrated circuit testing

ANDERSON TIMOTHY DAVID

Entry/exit control to/from a low power state in a complex multi level memory system

AGARWALA MANISHA

Trigger ordering for trace streams when multiple triggers accumulate

FLORES JOSE LUIS

Synchronized voltage scaling and device calibration

FLORES JOSE L

Address range comparator for detection of multi-size memory accesses with data matching qualification and full or partial overlap