Distributed power control for controlling power consumption based on detected activity of logic blocks

Abstract

An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

What is claimed is: 
     
       1. A power control apparatus comprising:
 a programmable global power controller, wherein said programmable global power controller is operable to reduce the power consumption in said logic blocks in response to detecting a lack of activity within said logic blocks; 
 a plurality of local power controllers; and 
 a plurality of logic blocks to be controlled, wherein said programmable global power controller is operable to reduce power consumption in at least one of said plurality of logic blocks in response to detecting a lack of activity within said at least one of said plurality of logic blocks, wherein at least one of said programmable global power controller and said plurality of local power controllers perform handshaking to determine the a power status for at least one of said plurality of logic blocks and said plurality of local power controllers, said handshaking comprising transmitting power status information pertaining to said at least one of said plurality of logic blocks from one of said plurality of local power controllers associated with said at least one of said plurality of logic blocks to said programmable global power controller, and wherein another one of said plurality of logic blocks is a CPU and said programmable global power controller is capable of powering down said CPU in response to a signal from a power controller separate from said CPU. 
 
     
     
       2. The power control apparatus of  claim 1 , wherein:
 said programmable global power controller is operable to communicate with said plurality of local power controllers. 
 
     
     
       3. The power control apparatus of  claim 2 , wherein:
 said one of said plurality of local power controller controllers associated with said at least one of said plurality of logic blocks is operable to control the power consumption of said at least one of said plurality of logic blocks. 
 
     
     
       4. The power control apparatus of  claim 2 , wherein:
 said programmable local global power controller is operable to control the power consumption by controlling the clock frequencies of the said plurality of logic blocks. 
 
     
     
       5. The power control apparatus of  claim 1 , wherein:
 said programmable global power controller is operable to restore the power consumption to normal in response an external request. 
 
     
     
       6. A method of power control comprising the steps of:
 generating an idle signal; 
 detecting a lack of activity within a first logic block of a plurality of logic blocks, each of said logic blocks associated with one of a plurality of local power controllers of which a first local power controller is associated with said first logic block; and 
 reducing the power consumption of the said first logic element associated with the idle signal block utilizing a programmable global power controller, wherein said programmable global power controller is operable to reduce the power consumption in said logic blocks in response to detecting a lack of activity within said logic blocks, a second logic block of said plurality of logic blocks is a CPU and said programmable global power controller is capable of powering down said CPU in response to a signal from a power controller separate from said CPU, and wherein at least one of said programmable global power controller and performs handshaking with said plurality of first local power controllers perform handshaking controller to determine the power status for at least one of said plurality of first logic blocks and said plurality of block by exchanging power status information with said first local power controllers controller. 
 
     
     
       7. The method of  claim 6  further comprising the steps of:
 detecting an internal or external request; and 
 restoring the a power state of the a logic element block associated with the request. 
 
     
     
       8. The method of  claim 6  wherein:
 said step of controlling reducing the power consumption of said first logic element block includes adjusting the a clock frequency of said first logic element block. 
 
     
     
       9. A power control apparatus comprising:
 an on-chip programmable global power controller;   a plurality of on-chip logic blocks to be controlled; and   a plurality of power controllers for controlling power to said plurality of on-chip logic blocks;   wherein said programmable global power controller is operable to reduce power consumption in at least one of said plurality of on-chip logic blocks in response to detecting a lack of activity within said at least one of said plurality of on-chip logic blocks;   wherein another one of said plurality of on-chip logic blocks is a CPU and said programmable global power controller is capable of powering down said CPU in response to a signal from a power controller separate from said CPU, and   wherein said programmable global power controller and said plurality of power controllers perform handshaking to determine the power status for said plurality of on-chip logic blocks by exchanging power status data bits.   
     
     
       10. The power control apparatus of claim 9, wherein:
 at least one of said plurality of power controllers is operable to control the power consumption of said at least one of said plurality of on-chip logic blocks by controlling a clock frequency associated with said at least one of said plurality of on-chip logic blocks.   
     
     
       11. The power control apparatus of claim 9, wherein:
 at least one of said plurality of power controllers is operable to control the power consumption by removing power to said at least one of said plurality of on-chip logic blocks.   
     
     
       12. The power control apparatus of claim 1 wherein said power controller separate from said CPU is an on-chip controller. 
     
     
       13. The power control apparatus of claim 6 wherein said power controller separate from said CPU is an on-chip controller. 
     
     
       14. The power control apparatus of claim 9 wherein said power controller separate from said CPU is an on-chip controller.